About the Execution of LoLA for UtilityControlRoom-PT-Z4T3N08
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
9748.088 | 3600000.00 | 546979.00 | 9695.80 | ???????TT??????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r445-smll-171701112100227.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is UtilityControlRoom-PT-Z4T3N08, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r445-smll-171701112100227
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.4M
-rw-r--r-- 1 mcc users 35K Apr 13 05:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 166K Apr 13 05:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 104K Apr 13 05:46 CTLFireability.txt
-rw-r--r-- 1 mcc users 385K Apr 13 05:46 CTLFireability.xml
-rw-r--r-- 1 mcc users 21K Apr 23 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Apr 23 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 41K Apr 23 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 123K Apr 23 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 76K Apr 13 06:05 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 368K Apr 13 06:05 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 142K Apr 13 06:01 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 541K Apr 13 06:01 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 5.7K Apr 23 08:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 13K Apr 23 08:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 255K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-05
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-07
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-08
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-09
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-10
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-11
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-12
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-13
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-14
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717106573793
FORMULA UtilityControlRoom-PT-Z4T3N08-LTLCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z4T3N08-LTLCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/SRCH) for 3 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 61 (type SKEL/SRCH) for 41 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 61 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 29
[[35mlola[0m][I] fired transitions : 29
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 19 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-05
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 62 (type SKEL/SRCH) for 44 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type SKEL/SRCH) for 9 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 63 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 35
[[35mlola[0m][I] fired transitions : 35
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 33 (type CNST) for 32 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-08
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 33 (type CNST) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 47 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/SRCH) for 29 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type SKEL/SRCH) for 35 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 29
[[35mlola[0m][I] fired transitions : 29
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/SRCH) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 247046
[[35mlola[0m][I] fired transitions : 528276
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 57 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-15
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 77
[[35mlola[0m][I] fired transitions : 104
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-14
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 40
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 47 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-13
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 40
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-12
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 40
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-11
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 9
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-10
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 235
[[35mlola[0m][I] fired transitions : 237
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-09
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 40
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 3/513 4/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 346747 m, 69349 m/sec, 799661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 8 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 8/513 8/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 885516 m, 107753 m/sec, 2166940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 13 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 13/513 13/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 1452208 m, 113338 m/sec, 3664689 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 18 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 18/513 18/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 2015500 m, 112658 m/sec, 5089497 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 23 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 23/513 23/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 2530787 m, 103057 m/sec, 6477661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 28 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 28/513 27/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 3007574 m, 95357 m/sec, 7817716 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 33 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 33/513 31/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 3481354 m, 94756 m/sec, 9140829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 38 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 38/513 35/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 3960834 m, 95896 m/sec, 10506134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 43 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 43/513 39/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 4436581 m, 95149 m/sec, 11839177 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 48 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 48/513 43/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 4905908 m, 93865 m/sec, 13147701 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 53 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 53/513 47/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 5355114 m, 89841 m/sec, 14436974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 58 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 58/513 51/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 5804514 m, 89880 m/sec, 15729411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 63 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 63/513 54/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 6228397 m, 84776 m/sec, 16954387 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 68 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 68/513 58/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 6661216 m, 86563 m/sec, 18226091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 73 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 73/513 62/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 7100216 m, 87800 m/sec, 19485907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 78 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 78/513 65/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 7528310 m, 85618 m/sec, 20718511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 83 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 83/513 69/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 7965870 m, 87512 m/sec, 21960215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 88 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 88/513 73/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 8383977 m, 83621 m/sec, 23179510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 93 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 93/513 76/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 8806911 m, 84586 m/sec, 24391436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 98 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 98/513 80/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 9221702 m, 82958 m/sec, 25600153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 103 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 103/513 83/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 9630120 m, 81683 m/sec, 26813096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 108 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 108/513 87/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 10034256 m, 80827 m/sec, 28001647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 113 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 113/513 90/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 10455244 m, 84197 m/sec, 29202454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 118 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 118/513 93/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 10850519 m, 79055 m/sec, 30390615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 123 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 123/513 97/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 11244578 m, 78811 m/sec, 31579295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 128 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 128/513 100/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 11644885 m, 80061 m/sec, 32772619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 133 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 133/513 104/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 12048668 m, 80756 m/sec, 33961557 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 138 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 138/513 107/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 12438136 m, 77893 m/sec, 35123683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 143 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 143/513 110/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 12824210 m, 77214 m/sec, 36282922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 148 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 148/513 113/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 13209455 m, 77049 m/sec, 37427832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 153 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 153/513 116/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 13591154 m, 76339 m/sec, 38581473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 158 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 158/513 120/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 13973950 m, 76559 m/sec, 39736518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 163 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 163/513 123/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 14360631 m, 77336 m/sec, 40896668 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 168 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 168/513 126/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 14750315 m, 77936 m/sec, 42029142 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 173 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 173/513 129/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 15125919 m, 75120 m/sec, 43156028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 178 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 178/513 132/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 15498090 m, 74434 m/sec, 44277021 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 183 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 183/513 136/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 15866616 m, 73705 m/sec, 45395597 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 188 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 188/513 139/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 16242688 m, 75214 m/sec, 46516294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 193 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 193/513 142/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 16619589 m, 75380 m/sec, 47630089 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 198 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 198/513 145/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 16986734 m, 73429 m/sec, 48739970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 203 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 203/513 148/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 17351280 m, 72909 m/sec, 49837669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 208 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 208/513 151/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 17729708 m, 75685 m/sec, 50953805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 213 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 213/513 154/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 18090778 m, 72214 m/sec, 52057126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 218 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 218/513 157/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 18451590 m, 72162 m/sec, 53153273 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 223 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 223/513 160/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 18811132 m, 71908 m/sec, 54235059 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 228 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 228/513 163/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 19181719 m, 74117 m/sec, 55348798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 233 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 233/513 166/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 19540043 m, 71664 m/sec, 56440225 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 238 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 238/513 169/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 19894132 m, 70817 m/sec, 57520220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 243 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 243/513 172/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 20262180 m, 73609 m/sec, 58604664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 248 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 248/513 175/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 20612477 m, 70059 m/sec, 59679730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 253 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 253/513 178/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 20960081 m, 69520 m/sec, 60747269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 258 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 258/513 181/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 21311976 m, 70379 m/sec, 61821476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 263 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 263/513 184/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 21663974 m, 70399 m/sec, 62881617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 268 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 268/513 187/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 22010393 m, 69283 m/sec, 63944920 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 273 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 273/513 190/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 22359337 m, 69788 m/sec, 65007221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 278 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 278/513 193/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 22702716 m, 68675 m/sec, 66073631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 283 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 283/513 195/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 23045180 m, 68492 m/sec, 67127998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 288 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 288/513 198/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 23390123 m, 68988 m/sec, 68193720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 293 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 293/513 201/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 23731601 m, 68295 m/sec, 69248078 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 298 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 298/513 204/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 24075357 m, 68751 m/sec, 70297198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 303 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 303/513 207/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 24414531 m, 67834 m/sec, 71357330 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 308 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 308/513 210/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 24756861 m, 68466 m/sec, 72400547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 313 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 313/513 212/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 25098639 m, 68355 m/sec, 73433066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 318 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 318/513 215/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 25439298 m, 68131 m/sec, 74485306 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 323 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 323/513 218/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 25776339 m, 67408 m/sec, 75528095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 328 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 328/513 221/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 26113999 m, 67532 m/sec, 76560312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 333 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 333/513 224/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 26445516 m, 66303 m/sec, 77588020 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 338 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 338/513 226/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 26783367 m, 67570 m/sec, 78629569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 343 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 343/513 229/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 27123777 m, 68082 m/sec, 79662256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 348 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 348/513 232/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 27457512 m, 66747 m/sec, 80693719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 353 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 353/513 235/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 27790831 m, 66663 m/sec, 81720693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 358 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 358/513 237/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 28121988 m, 66231 m/sec, 82737202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 363 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 363/513 240/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 28454676 m, 66537 m/sec, 83755422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 368 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 368/513 243/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 28785572 m, 66179 m/sec, 84779904 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 373 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 373/513 246/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 29112171 m, 65319 m/sec, 85797726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 378 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 378/513 248/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 29440499 m, 65665 m/sec, 86817560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 383 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 383/513 251/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 29768667 m, 65633 m/sec, 87834666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 388 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 388/513 254/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 30093613 m, 64989 m/sec, 88854489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 393 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 393/513 256/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 30418627 m, 65002 m/sec, 89869159 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 398 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 398/513 259/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 30743424 m, 64959 m/sec, 90868635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 403 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 403/513 262/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 31069196 m, 65154 m/sec, 91871717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 408 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 408/513 265/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 31399141 m, 65989 m/sec, 92878599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 413 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 413/513 267/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 31721300 m, 64431 m/sec, 93869911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 418 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 418/513 270/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 32040960 m, 63932 m/sec, 94873682 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 423 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 423/513 272/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 32362100 m, 64228 m/sec, 95862245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 428 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 428/513 275/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 32681264 m, 63832 m/sec, 96859941 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 433 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 433/513 278/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 33000651 m, 63877 m/sec, 97843315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 438 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 438/513 280/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 33317867 m, 63443 m/sec, 98838717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 443 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 443/513 283/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 33636651 m, 63756 m/sec, 99830097 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 448 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 448/513 286/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 33955105 m, 63690 m/sec, 100827424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 453 secs. Pages in use: 286
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 453/513 288/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 34296080 m, 68195 m/sec, 101857157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 458 secs. Pages in use: 288
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 458/513 291/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 34630901 m, 66964 m/sec, 102868149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 463 secs. Pages in use: 291
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 463/513 294/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 34947309 m, 63281 m/sec, 103855309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 468 secs. Pages in use: 294
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 468/513 296/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 35260521 m, 62642 m/sec, 104842033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 473 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 473/513 299/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 35572214 m, 62338 m/sec, 105824791 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 478 secs. Pages in use: 299
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 478/513 302/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 35884390 m, 62435 m/sec, 106812938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 483 secs. Pages in use: 302
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 483/513 304/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 36198219 m, 62765 m/sec, 107778302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 488 secs. Pages in use: 304
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 488/513 307/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 36511244 m, 62605 m/sec, 108760325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 493 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 493/513 309/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 36834536 m, 64658 m/sec, 109756690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 498 secs. Pages in use: 309
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 498/513 312/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 37149266 m, 62946 m/sec, 110733082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 503 secs. Pages in use: 312
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 503/513 315/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 37457238 m, 61594 m/sec, 111698482 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 508 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 508/513 317/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 37766003 m, 61753 m/sec, 112679694 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 513 secs. Pages in use: 317
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 513/513 320/2000 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 38077950 m, 62389 m/sec, 113642002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 518 secs. Pages in use: 320
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 27 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 523 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 9 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03
[[35mlola[0m][I] time limit : 512 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06
[[35mlola[0m][I] time limit : 3077 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 40
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 27 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 528 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02
[[35mlola[0m][I] time limit : 768 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 41
[[35mlola[0m][I] fired transitions : 42
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01
[[35mlola[0m][I] time limit : 1024 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 40
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00
[[35mlola[0m][I] time limit : 1536 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3459
[[35mlola[0m][I] fired transitions : 6964
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04
[[35mlola[0m][I] time limit : 3072 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for UtilityControlRoom-PT-Z4T3N08-LTLCardinality-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 203
[[35mlola[0m][I] fired transitions : 217
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 533 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 538 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 543 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 548 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 553 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 558 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 563 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 568 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 573 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 578 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 583 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 588 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 593 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 598 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 603 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 608 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 613 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 618 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 623 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 628 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 633 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 638 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 643 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 648 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 653 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 658 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 663 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 668 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 673 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 678 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 683 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 688 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 693 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 698 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 703 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 708 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 713 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 718 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 723 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 728 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 733 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 738 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 743 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 748 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 753 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 758 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 763 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 768 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 773 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 778 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 783 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 788 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 793 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 798 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 803 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 808 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 813 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 818 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 823 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 828 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 833 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 838 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 843 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 848 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 853 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 858 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 863 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 868 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 873 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 878 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 883 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 888 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 893 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 898 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 903 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 908 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 913 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 918 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 923 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 928 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 933 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 938 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 943 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 948 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 953 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 958 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 963 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 968 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 973 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 978 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 983 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 988 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 993 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 998 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1003 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1008 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1013 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1018 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1023 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1028 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1033 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1038 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1043 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1048 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1053 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1058 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1063 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1068 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1073 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1078 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1083 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1088 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1093 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1098 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1103 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1108 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1113 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1118 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1123 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1128 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1133 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1138 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1143 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1148 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1153 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1158 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1163 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1168 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1173 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1178 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1183 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1188 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1193 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1198 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1203 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1208 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1213 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1218 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1223 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1228 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1233 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1238 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1243 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1248 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1253 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1258 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1263 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1268 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1273 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1278 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1283 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1288 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1293 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1298 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1303 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1308 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1313 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1318 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1323 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1328 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1333 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1338 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1343 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1348 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1353 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1358 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1363 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1368 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1373 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1378 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1383 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1388 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1393 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1398 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1403 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1408 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1413 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1418 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1423 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1428 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1433 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1438 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1443 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1448 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1453 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1458 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1463 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1468 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1473 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1478 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1483 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1488 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1493 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1498 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1503 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1508 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1513 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1518 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1523 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1528 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1533 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1538 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1543 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1548 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1553 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1558 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1563 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-07: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1568 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z4T3N08-LTLCardinality-04: LTL false LTL model checker[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T3N08"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z4T3N08, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r445-smll-171701112100227"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T3N08.tgz
mv UtilityControlRoom-PT-Z4T3N08 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;