About the Execution of LoLA for UtilityControlRoom-PT-Z4T3N08
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.399 | 1485490.00 | 1466935.00 | 5196.80 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r445-smll-171701112100226.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is UtilityControlRoom-PT-Z4T3N08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r445-smll-171701112100226
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.4M
-rw-r--r-- 1 mcc users 35K Apr 13 05:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 166K Apr 13 05:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 104K Apr 13 05:46 CTLFireability.txt
-rw-r--r-- 1 mcc users 385K Apr 13 05:46 CTLFireability.xml
-rw-r--r-- 1 mcc users 21K Apr 23 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Apr 23 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 41K Apr 23 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 123K Apr 23 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 76K Apr 13 06:05 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 368K Apr 13 06:05 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 142K Apr 13 06:01 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 541K Apr 13 06:01 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 5.7K Apr 23 08:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 13K Apr 23 08:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 255K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-00
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-02
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-04
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-05
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-06
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-07
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-08
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-09
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-10
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-11
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-12
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-13
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-14
FORMULA_NAME UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717105072470
BK_STOP 1717106557960
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 3 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 119 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 55 (type EQUN) for 3 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 3 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 55 (type EQUN) for UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for 13 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 13 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03: AGEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 EFAGEF EXCL 4/211 3/2000 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01 607580 m, 121516 m/sec, 1263223 t fired, .
[[35mlola[0m][.] 61 EF STEQ 4/3599 0/5 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03: AGEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 EFAGEF EXCL 9/211 6/2000 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01 1215821 m, 121648 m/sec, 2666606 t fired, .
[[35mlola[0m][.] 61 EF STEQ 9/3599 0/5 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03: AGEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 EFAGEF EXCL 14/211 8/2000 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01 1753655 m, 107566 m/sec, 3945959 t fired, .
[[35mlola[0m][.] 61 EF STEQ 14/3599 0/5 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03 sara not yet started (preprocessing).
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[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03: AGEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 EFAGEF EXCL 19/211 10/2000 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01 2292344 m, 107737 m/sec, 5256596 t fired, .
[[35mlola[0m][.] 61 EF STEQ 19/3599 0/5 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03 sara not yet started (preprocessing).
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[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03: AGEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 EFAGEF EXCL 24/211 12/2000 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01 2834408 m, 108412 m/sec, 6599617 t fired, .
[[35mlola[0m][.] 61 EF STEQ 24/3599 0/5 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03 sara not yet started (preprocessing).
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[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-01: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-03: AGEF 0 1 1 0 2 0 0 0
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[[35mlola[0m][.] 23 CTL EXCL 5/405 3/2000 UtilityControlRoom-PT-Z4T3N08-CTLFireability-2024-06 353774 m, 70754 m/sec, 1142502 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T3N08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z4T3N08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r445-smll-171701112100226"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T3N08.tgz
mv UtilityControlRoom-PT-Z4T3N08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;