About the Execution of LoLA for UtilityControlRoom-PT-Z2T4N08
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 13259.212 | 816824.00 | 815126.00 | 1830.50 | F?FTFFTFTF?FFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r445-smll-171701112000204.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is UtilityControlRoom-PT-Z2T4N08, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r445-smll-171701112000204
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 21K Apr 13 05:10 CTLCardinality.txt
-rw-r--r-- 1 mcc users 120K Apr 13 05:10 CTLCardinality.xml
-rw-r--r-- 1 mcc users 27K Apr 13 05:07 CTLFireability.txt
-rw-r--r-- 1 mcc users 130K Apr 13 05:07 CTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 23 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 49K Apr 23 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 14K Apr 23 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 48K Apr 23 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 57K Apr 13 05:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 302K Apr 13 05:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 83K Apr 13 05:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 343K Apr 13 05:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.3K Apr 23 08:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.8K Apr 23 08:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 93K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z2T4N08-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717091378576
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N08-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m] [1m[33mUtilityControlRoom-PT-Z2T4N08-LTLFireability-01: LTL unknown AGGR[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T4N08-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T4N08-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T4N08-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[33mUtilityControlRoom-PT-Z2T4N08-LTLFireability-10: LTL unknown AGGR[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 816 secs. Pages in use: 530
BK_STOP 1717092195400
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 UtilityControlRoom-PT-Z2T4N08-LTLFireability-09
[[35mlola[0m][I] time limit : 133 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for UtilityControlRoom-PT-Z2T4N08-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 34
[[35mlola[0m][I] fired transitions : 34
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 UtilityControlRoom-PT-Z2T4N08-LTLFireability-10
[[35mlola[0m][I] time limit : 144 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/SRCH) for 25 UtilityControlRoom-PT-Z2T4N08-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/SRCH) for UtilityControlRoom-PT-Z2T4N08-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 34
[[35mlola[0m][I] fired transitions : 34
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 61 (type SKEL/SRCH) for 47 UtilityControlRoom-PT-Z2T4N08-LTLFireability-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type SKEL/SRCH) for UtilityControlRoom-PT-Z2T4N08-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 700
[[35mlola[0m][I] fired transitions : 1352
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 LTL EXCL 5/200 7/2000 UtilityControlRoom-PT-Z2T4N08-LTLFireability-10 928644 m, 185728 m/sec, 1939012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 LTL EXCL 10/200 13/2000 UtilityControlRoom-PT-Z2T4N08-LTLFireability-10 1762115 m, 166694 m/sec, 3855038 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 LTL EXCL 15/200 18/2000 UtilityControlRoom-PT-Z2T4N08-LTLFireability-10 2530641 m, 153705 m/sec, 5698371 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N08-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 LTL EXCL 20/200 23/2000 UtilityControlRoom-PT-Z2T4N08-LTLFireability-10 3286271 m, 151126 m/sec, 7555962 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N08-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] 55 LTL EXCL 10/936 12/2000 UtilityControlRoom-PT-Z2T4N08-LTLFireability-14 1757454 m, 168366 m/sec, 4183571 t fired, .
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[[35mlola[0m][.] 55 LTL EXCL 15/936 17/2000 UtilityControlRoom-PT-Z2T4N08-LTLFireability-14 2510847 m, 150678 m/sec, 6594542 t fired, .
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[[35mlola[0m][.] 55 LTL EXCL 20/936 22/2000 UtilityControlRoom-PT-Z2T4N08-LTLFireability-14 3250629 m, 147956 m/sec, 9208250 t fired, .
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[[35mlola[0m][.] 55 LTL EXCL 25/936 25/2000 UtilityControlRoom-PT-Z2T4N08-LTLFireability-14 3810478 m, 111969 m/sec, 11763334 t fired, .
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z2T4N08"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z2T4N08, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r445-smll-171701112000204"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z2T4N08.tgz
mv UtilityControlRoom-PT-Z2T4N08 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;