MCC'2024- Execution of r445-smll-171701112000195

About the Execution of LoLA for UtilityControlRoom-PT-Z2T4N06

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
6928.823	754478.00	760997.00	2237.90	FFTFFTTFFFFFTFFF	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r445-smll-171701112000195.qcow2', fmt=qcow2
Waiting for the VM to be ready (probing ssh)
..............................................................................
========================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is UtilityControlRoom-PT-Z2T4N06, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r445-smll-171701112000195
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 33K Apr 13 05:28 CTLCardinality.txt
-rw-r--r-- 1 mcc users 187K Apr 13 05:28 CTLCardinality.xml
-rw-r--r-- 1 mcc users 24K Apr 13 05:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 120K Apr 13 05:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 7.8K Apr 23 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 37K Apr 23 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 23 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 42K Apr 23 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 60K Apr 13 05:37 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 341K Apr 13 05:37 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 67K Apr 13 05:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 300K Apr 13 05:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.8K Apr 23 08:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.9K Apr 23 08:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 70K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-00
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-03
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-04
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-05
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-06
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-07
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-09
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-10
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-11
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-13
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-14
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1717089457521

FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-13 FALSE TECHNIQUES
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-00 FALSE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-04 FALSE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-14 FALSE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-03 FALSE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-15 FALSE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-11 FALSE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-10 FALSE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-09 FALSE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-07 FALSE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-06 TRUE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-05 TRUE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 TRUE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01 FALSE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08 FALSE
FORMULA UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12 TRUE
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 754 secs. Pages in use: 253

BK_STOP 1717090211999

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimi
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 56 (type SKEL/SRCH) for 7 UtilityControlRoo
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 56 (type SKEL/SRCH) for UtilityControlRoo
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 28
[[35mlola[0m][I] fired transitions : 28
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 44 (type CNST) for 43 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 44 (type CNST) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 57 (type SKEL/SRCH) for 0 UtilityControlRoo
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type SKEL/SRCH) for UtilityControlRoo
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 28
[[35mlola[0m][I] fired transitions : 28
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 58 (type SKEL/SRCH) for 19 UtilityControlRo
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type SKEL/SRCH) for UtilityControlRoo
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 0 UtilityControlRoom-PT-
[[35mlola[0m][I] time limit : 133 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 0 UtilityControlRoom-PT-
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 64 (type SKEL/SRCH) for 25 UtilityControlRo
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type SKEL/SRCH) for UtilityControlRoo
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 28
[[35mlola[0m][I] fired transitions : 28
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 19
[[35mlola[0m][I] fired transitions : 19
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 63 (type EQUN) for UtilityControlRoom-PT-
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : true
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 228
[[35mlola[0m][I] fired transitions : 267
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 67 (type SKEL/FNDP) for 46 UtilityControlRo
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/EQUN) for 46 UtilityControlRo
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/SRCH) for 46 UtilityControlRo
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/SRCH) for UtilityControlRoo
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 67 (type FNDP) for UtilityControlRoom-PT-
[[35mlola[0m][W] CANCELED task # 68 (type EQUN) for UtilityControlRoom-PT-
[[35mlola[0m][I] LAUNCH task # 70 (type SKEL/SRCH) for 34 UtilityControlRo
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type SKEL/SRCH) for UtilityControlRoo
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 28
[[35mlola[0m][I] fired transitions : 28
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 72 (type FNDP) for 46 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 46 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type SKEL/FNDP) for UtilityControlRoo
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 72 (type FNDP) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 73 (type EQUN) for UtilityControlRoom-PT-
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 68 (type SKEL/EQUN) for UtilityControlRoo
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 73 (type EQUN) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 14 LTL EXCL 5/299 7/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 14 LTL EXCL 10/299 14/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 14 LTL EXCL 15/299 19/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3429525
[[35mlola[0m][I] fired transitions : 12191748
[[35mlola[0m][I] time used : 19
[[35mlola[0m][I] memory pages used : 23
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 325 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 40054
[[35mlola[0m][I] fired transitions : 84815
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 55
[[35mlola[0m][I] fired transitions : 57
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 397 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 36
[[35mlola[0m][I] fired transitions : 36
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 447 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 137
[[35mlola[0m][I] fired transitions : 144
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 511 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 36
[[35mlola[0m][I] fired transitions : 36
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 596 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 19
[[35mlola[0m][I] fired transitions : 18
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 716 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 895 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 1/895 2/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 6/895 8/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 11/895 13/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 16/895 17/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 21/895 21/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 26/895 25/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 31/895 28/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 36/895 32/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 41/895 36/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 46/895 39/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 51/895 42/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 56/895 46/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 61/895 49/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 66/895 52/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 71/895 56/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 76/895 59/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 81/895 62/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 86/895 65/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 91/895 69/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 96/895 72/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 101/895 75/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 106/895 78/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 111/895 81/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 116/895 84/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 121/895 87/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 126/895 90/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 131/895 92/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 136/895 95/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 141/895 98/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 146/895 101/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 151/895 104/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 156/895 106/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 161/895 109/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 166/895 112/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 171/895 114/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 176/895 117/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 181/895 119/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 186/895 122/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 191/895 124/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 196/895 127/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 201/895 129/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 206/895 132/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 211/895 134/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 216/895 137/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 221/895 139/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 226/895 141/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 231/895 144/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 236/895 146/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 241/895 148/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 246/895 151/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 251/895 153/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 256/895 155/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 261/895 157/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 266/895 159/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 271/895 161/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 276/895 164/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 281/895 166/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 286/895 168/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 291/895 170/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 296/895 172/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 301/895 174/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 306/895 176/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 311/895 178/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 316/895 180/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 321/895 182/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 326/895 183/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 346 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 331/895 185/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 351 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 336/895 187/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 341/895 189/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 361 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 346/895 191/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 366 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 351/895 193/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 371 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 356/895 194/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 376 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 361/895 196/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 381 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 366/895 198/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 386 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 371/895 200/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 391 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 376/895 201/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 396 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 381/895 203/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 386/895 204/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 391/895 206/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 396/895 208/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 401/895 209/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 406/895 211/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 411/895 212/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 416/895 214/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 421/895 216/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 426/895 217/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 446 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 431/895 219/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 436/895 220/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 456 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 441/895 222/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 461 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 446/895 224/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 466 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 451/895 226/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 471 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 456/895 228/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 476 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 461/895 230/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 481 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 466/895 232/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 486 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 471/895 234/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 491 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 476/895 235/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 496 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 481/895 236/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 501 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 486/895 237/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 506 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 491/895 237/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 511 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 496/895 238/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 516 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 501/895 238/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 521 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 506/895 239/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 526 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 511/895 239/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 531 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 516/895 240/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 536 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 521/895 240/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 541 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 526/895 241/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 546 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 531/895 241/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 551 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 536/895 241/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 556 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 541/895 242/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 561 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 546/895 242/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 566 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 551/895 243/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 571 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 556/895 243/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 576 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 561/895 243/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 581 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 566/895 244/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 586 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 571/895 244/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 591 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 576/895 244/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 596 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 581/895 245/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 601 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 586/895 245/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 606 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 591/895 245/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 611 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 596/895 246/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 616 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 601/895 246/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 621 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 606/895 246/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 626 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 611/895 247/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 631 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 616/895 247/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 636 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 621/895 247/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 641 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 626/895 248/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 646 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 631/895 248/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 651 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 636/895 248/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 656 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 641/895 249/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 661 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 646/895 249/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 666 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 651/895 249/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 671 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 656/895 249/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 676 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 661/895 250/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 681 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 666/895 250/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 686 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 671/895 250/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 691 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 676/895 250/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 696 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 681/895 251/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 701 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 686/895 251/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 706 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 691/895 251/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 711 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 696/895 251/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 716 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 701/895 252/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 721 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 706/895 252/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 726 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 711/895 252/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 731 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 716/895 252/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 736 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 721/895 252/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 741 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 726/895 253/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 746 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-00:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-03:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-04:
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-05: LTL/CTL
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-06:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-07:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-09:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-10:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-11:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-13: INITIAL
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-14:
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T4N06-LTLCardinality-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-01:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-08:
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T4N06-LTLCardinality-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
[[35mlola[0m][.] 11 LTL EXCL 731/895 253/2000
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 751 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 38467126
[[35mlola[0m][I] fired transitions : 300922122
[[35mlola[0m][I] time used : 734
[[35mlola[0m][I] memory pages used : 253
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 7 UtilityControlRoom-PT-Z
[[35mlola[0m][I] time limit : 948 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for UtilityControlRoom-PT-Z
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 36
[[35mlola[0m][I] fired transitions : 36
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 1423 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 43
[[35mlola[0m][I] fired transitions : 43
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 UtilityControlRoom-PT
[[35mlola[0m][I] time limit : 2846 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for UtilityControlRoom-PT-
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... ============= COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m t[0m) default[0m .xml[0m m-PT-Z2T4N06-LTLCardinality-01 m-PT-Z2T4N06-LTLCardinality-01 -Z2T4N06-LTLCardinality-13 Z2T4N06-LTLCardinality-13 m-PT-Z2T4N06-LTLCardinality-00 m-PT-Z2T4N06-LTLCardinality-00 om-PT-Z2T4N06-LTLCardinality-05 m-PT-Z2T4N06-LTLCardinality-05 Z2T4N06-LTLCardinality-00 Z2T4N06-LTLCardinality-00 om-PT-Z2T4N06-LTLCardinality-07 m-PT-Z2T4N06-LTLCardinality-07 Z2T4N06-LTLCardinality-00 Z2T4N06-LTLCardinality-00 (obsolete) Z2T4N06-LTLCardinality-00 -Z2T4N06-LTLCardinality-04 Z2T4N06-LTLCardinality-04 -Z2T4N06-LTLCardinality-03 om-PT-Z2T4N06-LTLCardinality-14 om-PT-Z2T4N06-LTLCardinality-14 om-PT-Z2T4N06-LTLCardinality-14 m-PT-Z2T4N06-LTLCardinality-14 Z2T4N06-LTLCardinality-14 (obsolete) Z2T4N06-LTLCardinality-14 (obsolete) om-PT-Z2T4N06-LTLCardinality-10 m-PT-Z2T4N06-LTLCardinality-10 -Z2T4N06-LTLCardinality-14 -Z2T4N06-LTLCardinality-14 m-PT-Z2T4N06-LTLCardinality-14 Z2T4N06-LTLCardinality-14 Z2T4N06-LTLCardinality-14 (obsolete) m-PT-Z2T4N06-LTLCardinality-14 Z2T4N06-LTLCardinality-14 VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-03 1034121 m, 206824 m/sec, 2927275 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-03 2092745 m, 211724 m/sec, 6241674 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-03 2876430 m, 156737 m/sec, 9529903 t fired, . Z2T4N06-LTLCardinality-03 -Z2T4N06-LTLCardinality-15 Z2T4N06-LTLCardinality-15 -Z2T4N06-LTLCardinality-11 Z2T4N06-LTLCardinality-11 -Z2T4N06-LTLCardinality-10 Z2T4N06-LTLCardinality-10 -Z2T4N06-LTLCardinality-09 Z2T4N06-LTLCardinality-09 -Z2T4N06-LTLCardinality-07 Z2T4N06-LTLCardinality-07 -Z2T4N06-LTLCardinality-06 Z2T4N06-LTLCardinality-06 -Z2T4N06-LTLCardinality-05 Z2T4N06-LTLCardinality-05 -Z2T4N06-LTLCardinality-02 VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 262090 m, 52418 m/sec, 602321 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 1117881 m, 171158 m/sec, 3000143 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 1824264 m, 141276 m/sec, 5185378 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 2494847 m, 134116 m/sec, 7362344 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 3081533 m, 117337 m/sec, 9370164 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 3653836 m, 114460 m/sec, 11373212 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 4212139 m, 111660 m/sec, 13382019 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 4756987 m, 108969 m/sec, 15383478 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 5284783 m, 105559 m/sec, 17354663 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 5780048 m, 99053 m/sec, 19256562 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 6318681 m, 107726 m/sec, 21351386 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 6843663 m, 104996 m/sec, 23430527 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 7336564 m, 98580 m/sec, 25418199 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 7843287 m, 101344 m/sec, 27481068 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 8342235 m, 99789 m/sec, 29531280 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 8836643 m, 98881 m/sec, 31585217 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 9329024 m, 98476 m/sec, 33680656 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 9815468 m, 97288 m/sec, 35767259 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 10298137 m, 96533 m/sec, 37844375 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 10768977 m, 94168 m/sec, 39923126 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 11238219 m, 93848 m/sec, 41993327 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 11703149 m, 92986 m/sec, 44064594 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 12159901 m, 91350 m/sec, 46123805 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 12609221 m, 89864 m/sec, 48172060 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 13054777 m, 89111 m/sec, 50227270 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 13500359 m, 89116 m/sec, 52322361 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 13939672 m, 87862 m/sec, 54380385 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 14373213 m, 86708 m/sec, 56451132 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 14801656 m, 85688 m/sec, 58507763 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 15226023 m, 84873 m/sec, 60573429 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 15647431 m, 84281 m/sec, 62635475 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 16062910 m, 83095 m/sec, 64689000 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 16471596 m, 81737 m/sec, 66735056 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 16860586 m, 77798 m/sec, 68700357 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 17262469 m, 80376 m/sec, 70736098 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 17657356 m, 78977 m/sec, 72768599 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 18047981 m, 78125 m/sec, 74798570 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 18436086 m, 77621 m/sec, 76831571 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 18823221 m, 77427 m/sec, 78863301 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 19203913 m, 76138 m/sec, 80887226 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 19580671 m, 75351 m/sec, 82914389 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 19952605 m, 74386 m/sec, 84936993 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 20320983 m, 73675 m/sec, 86970895 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 20683160 m, 72435 m/sec, 88989195 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 21042096 m, 71787 m/sec, 91000923 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 21395550 m, 70690 m/sec, 93026721 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 21750194 m, 70928 m/sec, 95043111 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 22098082 m, 69577 m/sec, 97051217 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 22448099 m, 70003 m/sec, 99064798 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 22791644 m, 68709 m/sec, 101090424 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 23132653 m, 68201 m/sec, 103117704 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 23470103 m, 67490 m/sec, 105144783 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 23802685 m, 66516 m/sec, 107171133 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 24132642 m, 65991 m/sec, 109204176 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 24458317 m, 65135 m/sec, 111232471 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 24782364 m, 64809 m/sec, 113242613 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 25101517 m, 63830 m/sec, 115280658 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 25417292 m, 63155 m/sec, 117308337 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 25727820 m, 62105 m/sec, 119331166 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 26037222 m, 61880 m/sec, 121373570 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 26343007 m, 61157 m/sec, 123408586 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 26646978 m, 60794 m/sec, 125445459 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 26947925 m, 60189 m/sec, 127486511 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 27242063 m, 58827 m/sec, 129538817 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 27534961 m, 58579 m/sec, 131588191 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 27824296 m, 57867 m/sec, 133637587 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 28107177 m, 56576 m/sec, 135680367 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 28390368 m, 56638 m/sec, 137734576 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 28670390 m, 56004 m/sec, 139781463 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 28945561 m, 55034 m/sec, 141829930 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 29217611 m, 54410 m/sec, 143888895 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 29488877 m, 54253 m/sec, 145948956 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 29755377 m, 53300 m/sec, 148011258 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 30017857 m, 52496 m/sec, 150077915 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 30278245 m, 52077 m/sec, 152142867 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 30535245 m, 51400 m/sec, 154199554 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 30789361 m, 50823 m/sec, 156251641 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 31039468 m, 50021 m/sec, 158305946 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 31288586 m, 49823 m/sec, 160375099 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 31534245 m, 49131 m/sec, 162448810 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 31773303 m, 47811 m/sec, 164523072 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 32014523 m, 48244 m/sec, 166597355 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 32254191 m, 47933 m/sec, 168660222 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 32493405 m, 47842 m/sec, 170733742 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 32731934 m, 47705 m/sec, 172796987 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 32975475 m, 48708 m/sec, 174865971 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 33225305 m, 49966 m/sec, 176927757 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 33477636 m, 50466 m/sec, 179000211 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 33740047 m, 52482 m/sec, 181082038 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 34011287 m, 54248 m/sec, 183233859 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 34298191 m, 57380 m/sec, 185451717 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 34610732 m, 62508 m/sec, 187766618 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 34938971 m, 65647 m/sec, 190126995 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 35249963 m, 62198 m/sec, 192532490 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 35537928 m, 57593 m/sec, 194861771 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 35780265 m, 48467 m/sec, 197170822 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 35914279 m, 26802 m/sec, 199257046 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 35998824 m, 16909 m/sec, 201212263 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36078731 m, 15981 m/sec, 203136409 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36157254 m, 15704 m/sec, 205059178 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36235307 m, 15610 m/sec, 206990194 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36311808 m, 15300 m/sec, 208920193 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36387415 m, 15121 m/sec, 210847789 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36456678 m, 13852 m/sec, 212767225 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36523653 m, 13395 m/sec, 214694891 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36588278 m, 12925 m/sec, 216616527 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36647572 m, 11858 m/sec, 218539358 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36710319 m, 12549 m/sec, 220476082 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36770569 m, 12050 m/sec, 222410531 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36829844 m, 11855 m/sec, 224356450 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36887328 m, 11496 m/sec, 226309921 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36942802 m, 11094 m/sec, 228252053 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 36998469 m, 11133 m/sec, 230202287 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37051395 m, 10585 m/sec, 232152584 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37106092 m, 10939 m/sec, 234103693 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37157158 m, 10213 m/sec, 236056174 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37209908 m, 10550 m/sec, 238021332 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37263326 m, 10683 m/sec, 239987065 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37313497 m, 10034 m/sec, 241959782 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37364781 m, 10256 m/sec, 243936317 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37413879 m, 9819 m/sec, 245913965 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37464792 m, 10182 m/sec, 247903815 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37515202 m, 10082 m/sec, 249898875 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37563720 m, 9703 m/sec, 251888172 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37614583 m, 10172 m/sec, 253898050 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37664459 m, 9975 m/sec, 255907958 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37712289 m, 9566 m/sec, 257924663 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37761591 m, 9860 m/sec, 259953407 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37809488 m, 9579 m/sec, 261986913 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37854102 m, 8922 m/sec, 264012995 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37898921 m, 8963 m/sec, 266048244 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37943087 m, 8833 m/sec, 268091317 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 37985751 m, 8532 m/sec, 270139705 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38026432 m, 8136 m/sec, 272182332 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38067172 m, 8148 m/sec, 274236999 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38106270 m, 7819 m/sec, 276294451 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38144776 m, 7701 m/sec, 278358503 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38182514 m, 7547 m/sec, 280431483 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38219734 m, 7444 m/sec, 282512725 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38255771 m, 7207 m/sec, 284587975 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38291311 m, 7108 m/sec, 286679313 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38324498 m, 6637 m/sec, 288776467 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38356472 m, 6394 m/sec, 290895804 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38386257 m, 5957 m/sec, 293025293 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38414137 m, 5576 m/sec, 295182952 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38438740 m, 4920 m/sec, 297379648 t fired, . VALUE PRODUCED BY[0m CONJ false state space / EG[0m LTL false LTL model checker[0m LTL false LTL model checker[0m true LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 STATUS[0m UtilityControlRoom-PT-Z2T4N06-LTLCardinality-02 38459561 m, 4164 m/sec, 299674005 t fired, . Z2T4N06-LTLCardinality-02 2T4N06-LTLCardinality-01 2T4N06-LTLCardinality-01 -Z2T4N06-LTLCardinality-08 Z2T4N06-LTLCardinality-08 -Z2T4N06-LTLCardinality-12 Z2T4N06-LTLCardinality-12

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z2T4N06"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z2T4N06, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r445-smll-171701112000195"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z2T4N06.tgz
mv UtilityControlRoom-PT-Z2T4N06 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;