About the Execution of LoLA for UtilityControlRoom-PT-Z2T3N06
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 13417.884 | 1298926.00 | 1664294.00 | 3703.20 | FFTF?TTTFTFFT?FT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r445-smll-171701111900154.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is UtilityControlRoom-PT-Z2T3N06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r445-smll-171701111900154
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.3M
-rw-r--r-- 1 mcc users 13K Apr 13 05:48 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K Apr 13 05:48 CTLCardinality.xml
-rw-r--r-- 1 mcc users 24K Apr 13 05:47 CTLFireability.txt
-rw-r--r-- 1 mcc users 113K Apr 13 05:47 CTLFireability.xml
-rw-r--r-- 1 mcc users 7.9K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 37K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 8.3K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 33K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 43K Apr 13 05:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 242K Apr 13 05:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 96K Apr 13 05:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 422K Apr 13 05:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.0K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.2K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 70K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-00
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-02
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-04
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-05
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-06
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-07
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-08
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-09
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-10
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-11
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-12
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-13
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-14
FORMULA_NAME UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717077764006
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03: AXAG false state space /EXEF[0m
[[35mlola[0m] [1m[33mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-04: CTL unknown AGGR[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-08: F false state space / EG[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-11: DISJ false DISJ[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m] [1m[33mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-13: CTL unknown AGGR[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 1298 secs. Pages in use: 375
BK_STOP 1717079062932
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 33 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 120 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 30
[[35mlola[0m][I] fired transitions : 30
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/EQUN) for 9 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 56 (type SKEL/SRCH) for 9 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 24 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type SKEL/SRCH) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 60 (type EQUN) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03 (obsolete)
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 9 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/EQUN) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 62 (type EQUN) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-11: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 5/225 4/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-14 707171 m, 141434 m/sec, 1978421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-11: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 10/225 6/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-14 1332590 m, 125083 m/sec, 3976405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-11: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 15/225 9/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-14 1948275 m, 123137 m/sec, 6053532 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03: AXAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-11: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-03
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[[35mlola[0m][.] 47 CTL EXCL 5/224 4/5 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-14 848113 m, -3518102 m/sec, 2416548 t fired, .
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[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-13
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[[35mlola[0m][.] 44 CTL EXCL 5/240 4/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-13 737720 m, 147544 m/sec, 3145646 t fired, .
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[[35mlola[0m][.] 44 CTL EXCL 10/240 6/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-13 1343146 m, 121085 m/sec, 5960502 t fired, .
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[[35mlola[0m][.] 44 CTL EXCL 15/240 9/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-13 1904042 m, 112179 m/sec, 8661393 t fired, .
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[[35mlola[0m][.] 7 CTL EXCL 195/282 64/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-02 14996935 m, 56759 m/sec, 89328268 t fired, .
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[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-02
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-08
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[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-15
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[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-00
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[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-10
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[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-06
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[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-05
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[[35mlola[0m][.] 4 CTL EXCL 1/2621 1/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01 185274 m, 37054 m/sec, 449059 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 6/2621 5/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01 1054652 m, 173875 m/sec, 2820805 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 11/2621 8/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01 1813870 m, 151843 m/sec, 5005141 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 16/2621 12/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01 2531731 m, 143572 m/sec, 7139962 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 261/2621 92/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01 21273373 m, 23346 m/sec, 97197940 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 266/2621 92/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01 21388874 m, 23100 m/sec, 98791795 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 296/2621 95/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01 22034326 m, 20336 m/sec, 108512910 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 301/2621 95/2000 UtilityControlRoom-PT-Z2T3N06-CTLFireability-2024-01 22131081 m, 19351 m/sec, 110149182 t fired, .
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z2T3N06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z2T3N06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r445-smll-171701111900154"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z2T3N06.tgz
mv UtilityControlRoom-PT-Z2T3N06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;