About the Execution of LoLA for UtilityControlRoom-PT-Z2T3N04
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 226.479 | 10048.00 | 10606.00 | 184.30 | TFTFTFFTTFTFTTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r445-smll-171701111900146.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is UtilityControlRoom-PT-Z2T3N04, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r445-smll-171701111900146
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 24K Apr 13 05:09 CTLCardinality.txt
-rw-r--r-- 1 mcc users 153K Apr 13 05:09 CTLCardinality.xml
-rw-r--r-- 1 mcc users 22K Apr 13 05:06 CTLFireability.txt
-rw-r--r-- 1 mcc users 112K Apr 13 05:06 CTLFireability.xml
-rw-r--r-- 1 mcc users 6.8K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 32K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 29K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 23K Apr 13 05:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 137K Apr 13 05:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 72K Apr 13 05:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 332K Apr 13 05:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.6K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.3K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 47K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-00
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-01
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-02
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-03
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-05
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-06
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-07
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-08
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-09
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-10
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-11
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-12
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-13
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-14
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717077698940
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-00: EXEG true state space /EXEG[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04: CONJ true CONJ[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 9 secs. Pages in use: 1
BK_STOP 1717077708988
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 150 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 59 (type EQUN) for 0 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 12 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 59 (type EQUN) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 69 (type EQUN) for 12 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 66 (type EQUN) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 69 (type EQUN) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 204441
[[35mlola[0m][I] fired transitions : 1551181
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 56 (type EXCL) for 0 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 56 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 16
[[35mlola[0m][I] fired transitions : 16
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 121899
[[35mlola[0m][I] fired transitions : 570263
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 92883
[[35mlola[0m][I] fired transitions : 339783
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 73
[[35mlola[0m][I] fired transitions : 108
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 182
[[35mlola[0m][I] fired transitions : 244
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 18550
[[35mlola[0m][I] fired transitions : 128900
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 27 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 121099
[[35mlola[0m][I] fired transitions : 488687
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 23 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-00: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mUtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04: CONJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 1/359 1/2000 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-05 167532 m, 33506 m/sec, 649744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 24 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 208341
[[35mlola[0m][I] fired transitions : 2264481
[[35mlola[0m][I] time used : 3
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 15 (type EXCL) for 12 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 15 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 12 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 16
[[35mlola[0m][I] fired transitions : 32
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 12 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 16
[[35mlola[0m][I] fired transitions : 32
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 598 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 21168
[[35mlola[0m][I] fired transitions : 185409
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 718 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5510
[[35mlola[0m][I] fired transitions : 15177
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 898 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 19
[[35mlola[0m][I] fired transitions : 34
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 1197 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 104517
[[35mlola[0m][I] fired transitions : 892132
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 1796 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 84889
[[35mlola[0m][I] fired transitions : 684500
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 3591 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 519
[[35mlola[0m][I] fired transitions : 682
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z2T3N04"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z2T3N04, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r445-smll-171701111900146"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z2T3N04.tgz
mv UtilityControlRoom-PT-Z2T3N04 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;