Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r443-smll-171701109900178.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool greatspnxred
Input is UtilityControlRoom-PT-Z2T4N02, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r443-smll-171701109900178
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 620K
-rw-r--r-- 1 mcc users 9.2K Apr 13 05:11 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Apr 13 05:11 CTLCardinality.xml
-rw-r--r-- 1 mcc users 13K Apr 13 05:07 CTLFireability.txt
-rw-r--r-- 1 mcc users 73K Apr 13 05:07 CTLFireability.xml
-rw-r--r-- 1 mcc users 7.2K Apr 23 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 36K Apr 23 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Apr 23 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 23K Apr 23 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 23K Apr 13 05:13 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 163K Apr 13 05:13 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 23K Apr 13 05:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 109K Apr 13 05:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Apr 23 08:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.5K Apr 23 08:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 24K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-00
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-01
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-02
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-03
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-04
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-05
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-06
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-07
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-08
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-09
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-10
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-11
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-12
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-13
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-14
FORMULA_NAME UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717073123016

Invoking MCC driver with
BK_TOOL=greatspnxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z2T4N02
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool greatspn
Invoking reducer
Running Version 202405141337
[2024-05-30 12:45:25] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-05-30 12:45:25] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-30 12:45:25] [INFO ] Load time of PNML (sax parser for PT used): 90 ms
[2024-05-30 12:45:25] [INFO ] Transformed 38 places.
[2024-05-30 12:45:25] [INFO ] Transformed 54 transitions.
[2024-05-30 12:45:25] [INFO ] Parsed PT model containing 38 places and 54 transitions and 170 arcs in 312 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 37 ms.
Initial state reduction rules removed 4 formulas.
[2024-05-30 12:45:25] [INFO ] Reduced 2 identical enabling conditions.
[2024-05-30 12:45:25] [INFO ] Reduced 2 identical enabling conditions.
[2024-05-30 12:45:25] [INFO ] Reduced 2 identical enabling conditions.
Ensure Unique test removed 8 transitions
Reduce redundant transitions removed 8 transitions.
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 38 out of 38 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 46/46 transitions.
Applied a total of 0 rules in 27 ms. Remains 38 /38 variables (removed 0) and now considering 46/46 (removed 0) transitions.
// Phase 1: matrix 46 rows 38 cols
[2024-05-30 12:45:26] [INFO ] Computed 7 invariants in 9 ms
[2024-05-30 12:45:26] [INFO ] Implicit Places using invariants in 291 ms returned []
[2024-05-30 12:45:26] [INFO ] Invariant cache hit.
[2024-05-30 12:45:26] [INFO ] Implicit Places using invariants and state equation in 160 ms returned []
Implicit Place search using SMT with State Equation took 677 ms to find 0 implicit places.
Running 44 sub problems to find dead transitions.
[2024-05-30 12:45:26] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/36 variables, 2/2 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/36 variables, 0/2 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 2 (OVERLAPS) 2/38 variables, 5/7 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/38 variables, 0/7 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 4 (OVERLAPS) 46/84 variables, 38/45 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/84 variables, 0/45 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 6 (OVERLAPS) 0/84 variables, 0/45 constraints. Problems are: Problem set: 0 solved, 44 unsolved
No progress, stopping.
After SMT solving in domain Real declared 84/84 variables, and 45 constraints, problems are : Problem set: 0 solved, 44 unsolved in 1519 ms.
Refiners :[Positive P Invariants (semi-flows): 7/7 constraints, State Equation: 38/38 constraints, PredecessorRefiner: 44/44 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 44 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/36 variables, 2/2 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/36 variables, 0/2 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 2 (OVERLAPS) 2/38 variables, 5/7 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/38 variables, 0/7 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 4 (OVERLAPS) 46/84 variables, 38/45 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/84 variables, 44/89 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/84 variables, 0/89 constraints. Problems are: Problem set: 0 solved, 44 unsolved
At refinement iteration 7 (OVERLAPS) 0/84 variables, 0/89 constraints. Problems are: Problem set: 0 solved, 44 unsolved
No progress, stopping.
After SMT solving in domain Int declared 84/84 variables, and 89 constraints, problems are : Problem set: 0 solved, 44 unsolved in 1150 ms.
Refiners :[Positive P Invariants (semi-flows): 7/7 constraints, State Equation: 38/38 constraints, PredecessorRefiner: 44/44 constraints, Known Traps: 0/0 constraints]
After SMT, in 2792ms problems are : Problem set: 0 solved, 44 unsolved
Search for dead transitions found 0 dead transitions in 2815ms
Finished structural reductions in LTL mode , in 1 iterations and 3562 ms. Remains : 38/38 places, 46/46 transitions.
Support contains 38 out of 38 places after structural reductions.
[2024-05-30 12:45:29] [INFO ] Flatten gal took : 51 ms
[2024-05-30 12:45:29] [INFO ] Flatten gal took : 24 ms
[2024-05-30 12:45:30] [INFO ] Input system was already deterministic with 46 transitions.
RANDOM walk for 40000 steps (8 resets) in 1864 ms. (21 steps per ms) remains 2/29 properties
BEST_FIRST walk for 40002 steps (8 resets) in 397 ms. (100 steps per ms) remains 2/2 properties
BEST_FIRST walk for 40003 steps (8 resets) in 446 ms. (89 steps per ms) remains 2/2 properties
[2024-05-30 12:45:31] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/10 variables, 0/0 constraints. Problems are: Problem set: 0 solved, 2 unsolved
Problem AtomicPropp20 is UNSAT
Problem AtomicPropp21 is UNSAT
After SMT solving in domain Real declared 35/84 variables, and 5 constraints, problems are : Problem set: 2 solved, 0 unsolved in 36 ms.
Refiners :[Positive P Invariants (semi-flows): 5/7 constraints, State Equation: 0/38 constraints, PredecessorRefiner: 2/2 constraints, Known Traps: 0/0 constraints]
After SMT, in 49ms problems are : Problem set: 2 solved, 0 unsolved
Skipping Parikh replay, no witness traces provided.
Successfully simplified 2 atomic propositions for a total of 12 simplifications.
[2024-05-30 12:45:31] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 10 ms
[2024-05-30 12:45:31] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 11 ms
[2024-05-30 12:45:31] [INFO ] Input system was already deterministic with 46 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 46/46 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 34 transition count 42
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 34 transition count 42
Applied a total of 8 rules in 10 ms. Remains 34 /38 variables (removed 4) and now considering 42/46 (removed 4) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 34/38 places, 42/46 transitions.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:45:31] [INFO ] Input system was already deterministic with 42 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 46/46 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 46/46 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 46/46 transitions.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 6 ms
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 8 ms
[2024-05-30 12:45:31] [INFO ] Input system was already deterministic with 46 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 46/46 transitions.
Drop transitions (Trivial Post-Agglo cleanup.) removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 0 with 8 rules applied. Total rules applied 8 place count 38 transition count 38
Reduce places removed 8 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 12 rules applied. Total rules applied 20 place count 30 transition count 34
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 4 Pre rules applied. Total rules applied 20 place count 30 transition count 30
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 28 place count 26 transition count 30
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 29 place count 25 transition count 26
Iterating global reduction 2 with 1 rules applied. Total rules applied 30 place count 25 transition count 26
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 32 place count 23 transition count 24
Iterating global reduction 2 with 2 rules applied. Total rules applied 34 place count 23 transition count 24
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 36 place count 21 transition count 20
Iterating global reduction 2 with 2 rules applied. Total rules applied 38 place count 21 transition count 20
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 40 place count 19 transition count 18
Iterating global reduction 2 with 2 rules applied. Total rules applied 42 place count 19 transition count 18
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 44 place count 19 transition count 16
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 44 place count 19 transition count 14
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 48 place count 17 transition count 14
Applied a total of 48 rules in 33 ms. Remains 17 /38 variables (removed 21) and now considering 14/46 (removed 32) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 17/38 places, 14/46 transitions.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 2 ms
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 3 ms
[2024-05-30 12:45:31] [INFO ] Input system was already deterministic with 14 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 46/46 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 46/46 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 46/46 transitions.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 7 ms
[2024-05-30 12:45:31] [INFO ] Input system was already deterministic with 46 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 46/46 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 34 transition count 42
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 34 transition count 42
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 12 place count 32 transition count 40
Drop transitions (Redundant composition of simpler transitions.) removed 4 transitions
Redundant transition composition rules discarded 4 transitions
Iterating global reduction 0 with 4 rules applied. Total rules applied 16 place count 32 transition count 36
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 17 place count 31 transition count 32
Ensure Unique test removed 1 places
Iterating global reduction 0 with 2 rules applied. Total rules applied 19 place count 30 transition count 32
Applied a total of 19 rules in 12 ms. Remains 30 /38 variables (removed 8) and now considering 32/46 (removed 14) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 30/38 places, 32/46 transitions.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 3 ms
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 4 ms
[2024-05-30 12:45:31] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 46/46 transitions.
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 4 Pre rules applied. Total rules applied 0 place count 38 transition count 42
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 34 transition count 42
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 12 place count 32 transition count 40
Applied a total of 12 rules in 7 ms. Remains 32 /38 variables (removed 6) and now considering 40/46 (removed 6) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 32/38 places, 40/46 transitions.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 4 ms
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:45:31] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 46/46 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 34 transition count 42
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 34 transition count 42
Applied a total of 8 rules in 2 ms. Remains 34 /38 variables (removed 4) and now considering 42/46 (removed 4) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 34/38 places, 42/46 transitions.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 4 ms
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:45:31] [INFO ] Input system was already deterministic with 42 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 46/46 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 35 transition count 43
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 35 transition count 43
Applied a total of 6 rules in 2 ms. Remains 35 /38 variables (removed 3) and now considering 43/46 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 35/38 places, 43/46 transitions.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 4 ms
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 4 ms
[2024-05-30 12:45:31] [INFO ] Input system was already deterministic with 43 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 46/46 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 34 transition count 42
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 34 transition count 42
Applied a total of 8 rules in 2 ms. Remains 34 /38 variables (removed 4) and now considering 42/46 (removed 4) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 34/38 places, 42/46 transitions.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 4 ms
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 4 ms
[2024-05-30 12:45:31] [INFO ] Input system was already deterministic with 42 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 46/46 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 34 transition count 42
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 34 transition count 42
Applied a total of 8 rules in 2 ms. Remains 34 /38 variables (removed 4) and now considering 42/46 (removed 4) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 34/38 places, 42/46 transitions.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 4 ms
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:45:31] [INFO ] Input system was already deterministic with 42 transitions.
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 8 ms
[2024-05-30 12:45:31] [INFO ] Flatten gal took : 8 ms
[2024-05-30 12:45:31] [INFO ] Export to MCC of 10 properties in file /home/mcc/execution/CTLFireability.sr.xml took 6 ms.
[2024-05-30 12:45:31] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 38 places, 46 transitions and 138 arcs took 5 ms.
Total runtime 6019 ms.
There are residual formulas that ITS could not solve within timeout
----------------------------------------------------------------------
GreatSPN-meddly tool, MCC 2023
----------------------------------------------------------------------

Running UtilityControlRoom-PT-Z2T4N02

IS_COLORED=
IS_NUPN=

LOADING PETRI NET FILE /home/mcc/execution/412/model.pnml (PNML) ...
PNML VERSION 2009, P/T NET.
COLOR CLASSES: 0
CONSTANTS: 0
PLACES: 38
TRANSITIONS: 46
COLOR VARS: 0
MEASURES: 0
LOADING TIME: [User 0.000s, Sys 0.002s]


SAVING FILE /home/mcc/execution/412/model (.net / .def) ...
EXPORT TIME: [User 0.000s, Sys 0.000s]


----------------------------------------------------------------------
GreatSPN/Meddly.
Copyright (C) 1987-2022, University of Torino, Italy.
website: https://github.com/greatspn/SOURCES

Based on MEDDLY version 0.16.0
Copyright (C) 2009, Iowa State University Research Foundation, Inc.
website: http://meddly.sourceforge.net

Process ID: 542
MODEL NAME: /home/mcc/execution/412/model
38 places, 46 transitions.

Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Building monolithic NSF...
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-00 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-03 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-05 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-02 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-12 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-08 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-07 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-13 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-04 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T4N02-CTLFireability-2024-14 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
Ok.
EXITCODE: 0
----------------------------------------------------------------------

BK_STOP 1717073133007

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z2T4N02"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="greatspnxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool greatspnxred"
echo " Input is UtilityControlRoom-PT-Z2T4N02, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r443-smll-171701109900178"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z2T4N02.tgz
mv UtilityControlRoom-PT-Z2T4N02 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;