Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r443-smll-171701109900146.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool greatspnxred
Input is UtilityControlRoom-PT-Z2T3N04, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r443-smll-171701109900146
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 24K Apr 13 05:09 CTLCardinality.txt
-rw-r--r-- 1 mcc users 153K Apr 13 05:09 CTLCardinality.xml
-rw-r--r-- 1 mcc users 22K Apr 13 05:06 CTLFireability.txt
-rw-r--r-- 1 mcc users 112K Apr 13 05:06 CTLFireability.xml
-rw-r--r-- 1 mcc users 6.8K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 32K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 29K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 23K Apr 13 05:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 137K Apr 13 05:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 72K Apr 13 05:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 332K Apr 13 05:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.6K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.3K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 47K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-00
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-01
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-02
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-03
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-05
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-06
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-07
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-08
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-09
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-10
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-11
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-12
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-13
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-14
FORMULA_NAME UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717071660972

Invoking MCC driver with
BK_TOOL=greatspnxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z2T3N04
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool greatspn
Invoking reducer
Running Version 202405141337
[2024-05-30 12:21:03] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-05-30 12:21:03] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-30 12:21:03] [INFO ] Load time of PNML (sax parser for PT used): 119 ms
[2024-05-30 12:21:03] [INFO ] Transformed 72 places.
[2024-05-30 12:21:03] [INFO ] Transformed 108 transitions.
[2024-05-30 12:21:03] [INFO ] Parsed PT model containing 72 places and 108 transitions and 340 arcs in 360 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 45 ms.
[2024-05-30 12:21:03] [INFO ] Reduced 4 identical enabling conditions.
[2024-05-30 12:21:03] [INFO ] Reduced 4 identical enabling conditions.
Ensure Unique test removed 16 transitions
Reduce redundant transitions removed 16 transitions.
Support contains 72 out of 72 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Applied a total of 0 rules in 20 ms. Remains 72 /72 variables (removed 0) and now considering 92/92 (removed 0) transitions.
// Phase 1: matrix 92 rows 72 cols
[2024-05-30 12:21:04] [INFO ] Computed 11 invariants in 16 ms
[2024-05-30 12:21:04] [INFO ] Implicit Places using invariants in 338 ms returned []
[2024-05-30 12:21:04] [INFO ] Invariant cache hit.
[2024-05-30 12:21:04] [INFO ] Implicit Places using invariants and state equation in 239 ms returned []
Implicit Place search using SMT with State Equation took 774 ms to find 0 implicit places.
Running 88 sub problems to find dead transitions.
[2024-05-30 12:21:04] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/68 variables, 2/2 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/68 variables, 0/2 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 2 (OVERLAPS) 4/72 variables, 9/11 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/72 variables, 0/11 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 4 (OVERLAPS) 92/164 variables, 72/83 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/164 variables, 0/83 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 6 (OVERLAPS) 0/164 variables, 0/83 constraints. Problems are: Problem set: 0 solved, 88 unsolved
No progress, stopping.
After SMT solving in domain Real declared 164/164 variables, and 83 constraints, problems are : Problem set: 0 solved, 88 unsolved in 2523 ms.
Refiners :[Positive P Invariants (semi-flows): 11/11 constraints, State Equation: 72/72 constraints, PredecessorRefiner: 88/88 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 88 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/68 variables, 2/2 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/68 variables, 0/2 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 2 (OVERLAPS) 4/72 variables, 9/11 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/72 variables, 0/11 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 4 (OVERLAPS) 92/164 variables, 72/83 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/164 variables, 88/171 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/164 variables, 0/171 constraints. Problems are: Problem set: 0 solved, 88 unsolved
At refinement iteration 7 (OVERLAPS) 0/164 variables, 0/171 constraints. Problems are: Problem set: 0 solved, 88 unsolved
No progress, stopping.
After SMT solving in domain Int declared 164/164 variables, and 171 constraints, problems are : Problem set: 0 solved, 88 unsolved in 3263 ms.
Refiners :[Positive P Invariants (semi-flows): 11/11 constraints, State Equation: 72/72 constraints, PredecessorRefiner: 88/88 constraints, Known Traps: 0/0 constraints]
After SMT, in 5967ms problems are : Problem set: 0 solved, 88 unsolved
Search for dead transitions found 0 dead transitions in 5998ms
Finished structural reductions in LTL mode , in 1 iterations and 6864 ms. Remains : 72/72 places, 92/92 transitions.
Support contains 72 out of 72 places after structural reductions.
[2024-05-30 12:21:11] [INFO ] Flatten gal took : 76 ms
[2024-05-30 12:21:11] [INFO ] Flatten gal took : 57 ms
[2024-05-30 12:21:11] [INFO ] Input system was already deterministic with 92 transitions.
Reduction of identical properties reduced properties to check from 61 to 58
RANDOM walk for 40000 steps (8 resets) in 3022 ms. (13 steps per ms) remains 2/58 properties
BEST_FIRST walk for 40004 steps (8 resets) in 950 ms. (42 steps per ms) remains 2/2 properties
BEST_FIRST walk for 40004 steps (8 resets) in 127 ms. (312 steps per ms) remains 2/2 properties
[2024-05-30 12:21:13] [INFO ] Invariant cache hit.
Problem AtomicPropp18 is UNSAT
At refinement iteration 0 (INCLUDED_ONLY) 0/41 variables, 0/0 constraints. Problems are: Problem set: 1 solved, 1 unsolved
Problem AtomicPropp43 is UNSAT
After SMT solving in domain Real declared 72/164 variables, and 11 constraints, problems are : Problem set: 2 solved, 0 unsolved in 51 ms.
Refiners :[Positive P Invariants (semi-flows): 11/11 constraints, State Equation: 0/72 constraints, PredecessorRefiner: 2/2 constraints, Known Traps: 0/0 constraints]
After SMT, in 85ms problems are : Problem set: 2 solved, 0 unsolved
Skipping Parikh replay, no witness traces provided.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 23 ms
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 14 ms
[2024-05-30 12:21:13] [INFO ] Input system was already deterministic with 92 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 64 transition count 84
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 64 transition count 84
Applied a total of 16 rules in 17 ms. Remains 64 /72 variables (removed 8) and now considering 84/92 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 64/72 places, 84/92 transitions.
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 11 ms
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 11 ms
[2024-05-30 12:21:13] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Applied a total of 0 rules in 1 ms. Remains 72 /72 variables (removed 0) and now considering 92/92 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 72/72 places, 92/92 transitions.
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 12 ms
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 13 ms
[2024-05-30 12:21:13] [INFO ] Input system was already deterministic with 92 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Applied a total of 0 rules in 10 ms. Remains 72 /72 variables (removed 0) and now considering 92/92 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 72/72 places, 92/92 transitions.
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 12 ms
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 13 ms
[2024-05-30 12:21:13] [INFO ] Input system was already deterministic with 92 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Drop transitions (Trivial Post-Agglo cleanup.) removed 16 transitions
Trivial Post-agglo rules discarded 16 transitions
Performed 16 trivial Post agglomeration. Transition count delta: 16
Iterating post reduction 0 with 16 rules applied. Total rules applied 16 place count 72 transition count 76
Reduce places removed 16 places and 0 transitions.
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 1 with 24 rules applied. Total rules applied 40 place count 56 transition count 68
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 41 place count 55 transition count 60
Iterating global reduction 2 with 1 rules applied. Total rules applied 42 place count 55 transition count 60
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 46 place count 51 transition count 56
Iterating global reduction 2 with 4 rules applied. Total rules applied 50 place count 51 transition count 56
Applied a total of 50 rules in 35 ms. Remains 51 /72 variables (removed 21) and now considering 56/92 (removed 36) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 51/72 places, 56/92 transitions.
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 7 ms
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 14 ms
[2024-05-30 12:21:13] [INFO ] Input system was already deterministic with 56 transitions.
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 64 transition count 84
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 64 transition count 84
Applied a total of 16 rules in 4 ms. Remains 64 /72 variables (removed 8) and now considering 84/92 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 64/72 places, 84/92 transitions.
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 9 ms
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 10 ms
[2024-05-30 12:21:13] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 64 transition count 84
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 64 transition count 84
Applied a total of 16 rules in 4 ms. Remains 64 /72 variables (removed 8) and now considering 84/92 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 64/72 places, 84/92 transitions.
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 9 ms
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 9 ms
[2024-05-30 12:21:13] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Applied a total of 0 rules in 1 ms. Remains 72 /72 variables (removed 0) and now considering 92/92 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 72/72 places, 92/92 transitions.
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 10 ms
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 11 ms
[2024-05-30 12:21:13] [INFO ] Input system was already deterministic with 92 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Applied a total of 0 rules in 3 ms. Remains 72 /72 variables (removed 0) and now considering 92/92 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 72/72 places, 92/92 transitions.
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 10 ms
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 6 ms
[2024-05-30 12:21:13] [INFO ] Input system was already deterministic with 92 transitions.
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 7 place count 65 transition count 85
Iterating global reduction 0 with 7 rules applied. Total rules applied 14 place count 65 transition count 85
Applied a total of 14 rules in 4 ms. Remains 65 /72 variables (removed 7) and now considering 85/92 (removed 7) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 65/72 places, 85/92 transitions.
[2024-05-30 12:21:13] [INFO ] Flatten gal took : 4 ms
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:21:14] [INFO ] Input system was already deterministic with 85 transitions.
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 6 place count 66 transition count 86
Iterating global reduction 0 with 6 rules applied. Total rules applied 12 place count 66 transition count 86
Applied a total of 12 rules in 4 ms. Remains 66 /72 variables (removed 6) and now considering 86/92 (removed 6) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 66/72 places, 86/92 transitions.
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:21:14] [INFO ] Input system was already deterministic with 86 transitions.
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 64 transition count 84
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 64 transition count 84
Applied a total of 16 rules in 4 ms. Remains 64 /72 variables (removed 8) and now considering 84/92 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 64/72 places, 84/92 transitions.
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:21:14] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 64 transition count 84
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 64 transition count 84
Applied a total of 16 rules in 4 ms. Remains 64 /72 variables (removed 8) and now considering 84/92 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 64/72 places, 84/92 transitions.
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:21:14] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Performed 14 Post agglomeration using F-continuation condition.Transition count delta: 14
Iterating post reduction 0 with 14 rules applied. Total rules applied 14 place count 72 transition count 78
Reduce places removed 14 places and 0 transitions.
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 21 rules applied. Total rules applied 35 place count 58 transition count 71
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 6 Pre rules applied. Total rules applied 35 place count 58 transition count 65
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 2 with 12 rules applied. Total rules applied 47 place count 52 transition count 65
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 48 place count 51 transition count 64
Iterating global reduction 2 with 1 rules applied. Total rules applied 49 place count 51 transition count 64
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 57 place count 47 transition count 60
Applied a total of 57 rules in 19 ms. Remains 47 /72 variables (removed 25) and now considering 60/92 (removed 32) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 47/72 places, 60/92 transitions.
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 3 ms
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 3 ms
[2024-05-30 12:21:14] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 7 place count 65 transition count 85
Iterating global reduction 0 with 7 rules applied. Total rules applied 14 place count 65 transition count 85
Applied a total of 14 rules in 3 ms. Remains 65 /72 variables (removed 7) and now considering 85/92 (removed 7) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 65/72 places, 85/92 transitions.
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:21:14] [INFO ] Input system was already deterministic with 85 transitions.
Starting structural reductions in LTL mode, iteration 0 : 72/72 places, 92/92 transitions.
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 6 place count 66 transition count 86
Iterating global reduction 0 with 6 rules applied. Total rules applied 12 place count 66 transition count 86
Applied a total of 12 rules in 3 ms. Remains 66 /72 variables (removed 6) and now considering 86/92 (removed 6) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 66/72 places, 86/92 transitions.
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 5 ms
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 6 ms
[2024-05-30 12:21:14] [INFO ] Input system was already deterministic with 86 transitions.
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 9 ms
[2024-05-30 12:21:14] [INFO ] Flatten gal took : 10 ms
[2024-05-30 12:21:14] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 15 ms.
[2024-05-30 12:21:14] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 72 places, 92 transitions and 276 arcs took 7 ms.
Total runtime 10874 ms.
There are residual formulas that ITS could not solve within timeout
----------------------------------------------------------------------
GreatSPN-meddly tool, MCC 2023
----------------------------------------------------------------------

Running UtilityControlRoom-PT-Z2T3N04

IS_COLORED=
IS_NUPN=

LOADING PETRI NET FILE /home/mcc/execution/413/model.pnml (PNML) ...
PNML VERSION 2009, P/T NET.
COLOR CLASSES: 0
CONSTANTS: 0
PLACES: 72
TRANSITIONS: 92
COLOR VARS: 0
MEASURES: 0
LOADING TIME: [User 0.003s, Sys 0.001s]


SAVING FILE /home/mcc/execution/413/model (.net / .def) ...
EXPORT TIME: [User 0.000s, Sys 0.001s]


----------------------------------------------------------------------
GreatSPN/Meddly.
Copyright (C) 1987-2022, University of Torino, Italy.
website: https://github.com/greatspn/SOURCES

Based on MEDDLY version 0.16.0
Copyright (C) 2009, Iowa State University Research Foundation, Inc.
website: http://meddly.sourceforge.net

Process ID: 550
MODEL NAME: /home/mcc/execution/413/model
72 places, 92 transitions.

Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Building monolithic NSF...
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-00 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-03 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-01 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-05 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-02 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-04 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-08 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-07 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-06 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-10 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-14 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-11 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-09 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-12 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA UtilityControlRoom-PT-Z2T3N04-CTLFireability-2024-15 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
Ok.
EXITCODE: 0
----------------------------------------------------------------------

BK_STOP 1717071677018

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z2T3N04"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="greatspnxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool greatspnxred"
echo " Input is UtilityControlRoom-PT-Z2T3N04, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r443-smll-171701109900146"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z2T3N04.tgz
mv UtilityControlRoom-PT-Z2T3N04 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;