Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575300436.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC10000vD, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575300436
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 6.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 13 07:11 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Apr 13 07:11 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 13 07:11 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Apr 13 07:11 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717188638878

FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-00: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-01: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-02: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-03: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-04: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-05: LTL true LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-06: CONJ false LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-07: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-08: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-09: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-10: CONJ false findpath
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-11: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-12: AG false findpath
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-13: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-14: LTL true LTL model checker
[lola] TwoPhaseLocking-PT-nC10000vD-LTLFireability-15: LTL false LTL model checker
[lola]
[lola] Time elapsed: 98 secs. Pages in use: 326

BK_STOP 1717188737654

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC10000vD-LTLFireability-02
[lola][I] time limit : 200 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 64 (type EQUN) for 34 TwoPhaseLocking-PT-nC10000vD-LTLFireability-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 61 (type FNDP) for 34 TwoPhaseLocking-PT-nC10000vD-LTLFireability-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 62 (type EQUN) for 34 TwoPhaseLocking-PT-nC10000vD-LTLFireability-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 61 (type FNDP) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-10
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 62 (type EQUN) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-10 (obsolete)
[lola][W] CANCELED task # 64 (type EQUN) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-10 (obsolete)
[lola][I] LAUNCH task # 66 (type FNDP) for 44 TwoPhaseLocking-PT-nC10000vD-LTLFireability-12
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 67 (type EQUN) for 44 TwoPhaseLocking-PT-nC10000vD-LTLFireability-12
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 62 (type EQUN) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-10
[lola][I] result : true
[lola][I] FINISHED task # 66 (type FNDP) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-12
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 67 (type EQUN) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-12 (obsolete)
[lola][I] FINISHED task # 64 (type EQUN) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-10
[lola][I] result : true
[lola][I] FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-02
[lola][I] result : false
[lola][I] markings : 20004
[lola][I] fired transitions : 20005
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 51 (type EXCL) for 50 TwoPhaseLocking-PT-nC10000vD-LTLFireability-14
[lola][I] time limit : 257 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 51 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-14
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 48 (type EXCL) for 47 TwoPhaseLocking-PT-nC10000vD-LTLFireability-13
[lola][I] time limit : 276 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 67 (type EQUN) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-12
[lola][I] result : true
[lola][I] FINISHED task # 48 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-13
[lola][I] result : false
[lola][I] markings : 20001
[lola][I] fired transitions : 20001
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 42 (type EXCL) for 41 TwoPhaseLocking-PT-nC10000vD-LTLFireability-11
[lola][I] time limit : 300 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 42 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-11
[lola][I] result : false
[lola][I] markings : 20001
[lola][I] fired transitions : 20001
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 29 (type EXCL) for 28 TwoPhaseLocking-PT-nC10000vD-LTLFireability-08
[lola][I] time limit : 327 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 29 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-08
[lola][I] result : false
[lola][I] markings : 35000
[lola][I] fired transitions : 35000
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 23 (type EXCL) for 18 TwoPhaseLocking-PT-nC10000vD-LTLFireability-06
[lola][I] time limit : 360 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 23 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-06
[lola][I] result : false
[lola][I] markings : 20001
[lola][I] fired transitions : 20001
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC10000vD-LTLFireability-04
[lola][I] time limit : 450 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-04
[lola][I] result : false
[lola][I] markings : 20001
[lola][I] fired transitions : 20001
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC10000vD-LTLFireability-01
[lola][I] time limit : 514 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-04: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-06: CONJ false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-08: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-10: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-12: AG false findpath
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-13: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-14: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 4 LTL EXCL 5/514 24/2000 TwoPhaseLocking-PT-nC10000vD-LTLFireability-01 3535140 m, 707028 m/sec, 5299648 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 24
[lola][.] # running tasks: 1 of 4. Visible: 16
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[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-10: CONJ false findpath
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[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-14: LTL true LTL model checker
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[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 54 LTL EXCL 28/713 133/2000 TwoPhaseLocking-PT-nC10000vD-LTLFireability-15 20463740 m, 744820 m/sec, 30682058 t fired, .
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[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-10: CONJ false findpath
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[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-12: AG false findpath
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-13: LTL false LTL model checker
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[lola][.] 54 LTL EXCL 33/713 158/2000 TwoPhaseLocking-PT-nC10000vD-LTLFireability-15 24198384 m, 746928 m/sec, 36283761 t fired, .
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[lola][.] 54 LTL EXCL 38/713 182/2000 TwoPhaseLocking-PT-nC10000vD-LTLFireability-15 27922402 m, 744803 m/sec, 41869541 t fired, .
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[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-12: AG false findpath
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[lola][.] 54 LTL EXCL 43/713 207/2000 TwoPhaseLocking-PT-nC10000vD-LTLFireability-15 31718315 m, 759182 m/sec, 47563225 t fired, .
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[lola][.] 54 LTL EXCL 48/713 231/2000 TwoPhaseLocking-PT-nC10000vD-LTLFireability-15 35471865 m, 750710 m/sec, 53192976 t fired, .
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[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-12: AG false findpath
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-13: LTL false LTL model checker
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[lola][.] 54 LTL EXCL 53/713 256/2000 TwoPhaseLocking-PT-nC10000vD-LTLFireability-15 39315603 m, 768747 m/sec, 58957246 t fired, .
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[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-10: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-12: AG false findpath
[lola][.] TwoPhaseLocking-PT-nC10000vD-LTLFireability-13: LTL false LTL model checker
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[lola][.] 54 LTL EXCL 58/713 281/2000 TwoPhaseLocking-PT-nC10000vD-LTLFireability-15 43211678 m, 779215 m/sec, 64802459 t fired, .
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[lola][.] 54 LTL EXCL 63/713 308/2000 TwoPhaseLocking-PT-nC10000vD-LTLFireability-15 47252950 m, 808254 m/sec, 70862367 t fired, .
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[lola][I] FINISHED task # 54 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-15
[lola][I] result : false
[lola][I] markings : 50020001
[lola][I] fired transitions : 75015001
[lola][I] time used : 66
[lola][I] memory pages used : 326
[lola][I] LAUNCH task # 32 (type EXCL) for 31 TwoPhaseLocking-PT-nC10000vD-LTLFireability-09
[lola][I] time limit : 875 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 32 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-09
[lola][I] result : false
[lola][I] markings : 15016
[lola][I] fired transitions : 15040
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 26 (type EXCL) for 25 TwoPhaseLocking-PT-nC10000vD-LTLFireability-07
[lola][I] time limit : 1167 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 26 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-07
[lola][I] result : false
[lola][I] markings : 20003
[lola][I] fired transitions : 20004
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC10000vD-LTLFireability-05
[lola][I] time limit : 1751 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 16 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-05
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC10000vD-LTLFireability-03
[lola][I] time limit : 3502 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-LTLFireability-03
[lola][I] result : false
[lola][I] markings : 15002
[lola][I] fired transitions : 15003
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC10000vD"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC10000vD, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575300436"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC10000vD.tgz
mv TwoPhaseLocking-PT-nC10000vD execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;