About the Execution of LoLA for TwoPhaseLocking-PT-nC10000vD
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16160.567 | 282634.00 | 361942.00 | 734.80 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575300434.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC10000vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575300434
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 6.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 13 07:11 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Apr 13 07:11 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 13 07:11 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Apr 13 07:11 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-00
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-03
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-04
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-05
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-06
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-07
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-10
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-13
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717188023852
BK_STOP 1717188306486
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 69 (type EQUN) for 41 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 24 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 24 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 6 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 71 (type EQUN) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 6 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type EQUN) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/199 12/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 2734630 m, 546926 m/sec, 5410158 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/199 23/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 5253578 m, 503789 m/sec, 10415273 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 15/199 33/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 7689322 m, 487148 m/sec, 15259783 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 20/199 44/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 10081568 m, 478449 m/sec, 20020379 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 25/199 54/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 12474254 m, 478537 m/sec, 24783670 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 30/199 64/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 14837843 m, 472717 m/sec, 29490358 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 35/199 74/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 17163700 m, 465171 m/sec, 34122605 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 40/199 84/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 19464893 m, 460238 m/sec, 38708025 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 45/199 94/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 21739770 m, 454975 m/sec, 43240141 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 50/199 103/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 23987612 m, 449568 m/sec, 47719989 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 55/199 113/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 26227886 m, 448054 m/sec, 52184200 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 60/199 122/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 28457600 m, 445942 m/sec, 56628091 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 65/199 132/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 30671580 m, 442796 m/sec, 61041431 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 70/199 141/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 32884470 m, 442578 m/sec, 65452231 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 75/199 151/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 35061870 m, 435480 m/sec, 69793095 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 80/199 160/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 37219522 m, 431530 m/sec, 74095602 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 85/199 169/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 39379732 m, 432042 m/sec, 78402981 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 90/199 178/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 41543004 m, 432654 m/sec, 82716241 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 95/199 187/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 43656944 m, 422788 m/sec, 86932108 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 100/199 196/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 45770187 m, 422648 m/sec, 91146390 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 105/199 205/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 47861403 m, 418243 m/sec, 95316425 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 110/199 214/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 49951634 m, 418046 m/sec, 99484300 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 115/199 223/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 52045969 m, 418867 m/sec, 103661798 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 120/199 232/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 54140934 m, 418993 m/sec, 107840409 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 125/199 241/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 56199059 m, 411625 m/sec, 111945194 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 130/199 250/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 58267737 m, 413735 m/sec, 116070935 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 135/199 259/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 60332022 m, 412857 m/sec, 120189435 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 140/199 268/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 62399297 m, 413455 m/sec, 124312099 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 145/199 277/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 64442078 m, 408556 m/sec, 128387356 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 150/199 285/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 66464216 m, 404427 m/sec, 132421219 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 155/199 294/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 68460546 m, 399266 m/sec, 136404641 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 160/199 302/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 70465849 m, 401060 m/sec, 140405115 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 165/199 311/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 72376339 m, 382098 m/sec, 144215375 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 170/199 319/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 74402383 m, 405208 m/sec, 148258448 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 175/199 328/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 76445525 m, 408628 m/sec, 152333814 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 180/199 337/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 78479289 m, 406752 m/sec, 156392163 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 185/199 345/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 80487516 m, 401645 m/sec, 160399361 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 190/199 354/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 82510828 m, 404662 m/sec, 164436656 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 195/199 363/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01 84533152 m, 404464 m/sec, 168471900 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11: AXAF 0 1 0 0 2 0 0 0
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[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01
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[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-11
[[35mlola[0m][I] result : false
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 54 CTL EXCL 5/212 7/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15 1703340 m, 340668 m/sec, 5092192 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 54 CTL EXCL 10/212 14/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15 3272382 m, 313808 m/sec, 10359547 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 54 CTL EXCL 15/212 20/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15 4824931 m, 310509 m/sec, 15740824 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 54 CTL EXCL 20/212 27/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15 6448627 m, 324739 m/sec, 21102470 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-08: DISJ 0 3 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC10000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 54 CTL EXCL 25/212 32/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15 7883450 m, 286964 m/sec, 26680947 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 30/212 39/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15 9447762 m, 312862 m/sec, 31791830 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 50/212 63/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15 15483998 m, 262731 m/sec, 52270391 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 55/212 69/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15 17022905 m, 307781 m/sec, 57204119 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 60/212 75/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15 18468732 m, 289165 m/sec, 62128414 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 75/212 92/2000 TwoPhaseLocking-PT-nC10000vD-CTLFireability-2023-15 22678121 m, 273099 m/sec, 77001645 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC10000vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC10000vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575300434"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC10000vD.tgz
mv TwoPhaseLocking-PT-nC10000vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;