About the Execution of LoLA for TwoPhaseLocking-PT-nC05000vN
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.188 | 272376.00 | 200339.00 | 1787.30 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575300426.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC05000vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575300426
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 444K
-rw-r--r-- 1 mcc users 7.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.1K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 19 07:39 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 19 19:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.3K Apr 13 07:23 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 85K Apr 13 07:23 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 13 07:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 100K Apr 13 07:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717187487282
BK_STOP 1717187759658
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 21 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 33 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 27 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 5/189 23/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 5378469 m, 1075693 m/sec, 5392370 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 10/189 45/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 10617392 m, 1047784 m/sec, 10641564 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 15/189 66/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 15581314 m, 992784 m/sec, 15615849 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 20/189 87/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 20633950 m, 1010527 m/sec, 20679115 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 25/189 108/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 25629484 m, 999106 m/sec, 25685224 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 30/189 128/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 30396182 m, 953339 m/sec, 30462072 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 35/189 148/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 35198832 m, 960530 m/sec, 35274997 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 40/189 168/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 39993514 m, 958936 m/sec, 40079999 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 45/189 189/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 44811629 m, 963623 m/sec, 44908533 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 19 CTL EXCL 50/189 209/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 49568726 m, 951419 m/sec, 49675961 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 55/189 228/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 54326741 m, 951603 m/sec, 54444355 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 60/189 248/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 59097028 m, 954057 m/sec, 59225093 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 65/189 268/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 63837526 m, 948099 m/sec, 63976016 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 70/189 288/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 68568488 m, 946192 m/sec, 68717428 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 75/189 308/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 73334120 m, 953126 m/sec, 73493625 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 80/189 327/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 77891238 m, 911423 m/sec, 78060883 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 85/189 347/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 82563524 m, 934457 m/sec, 82743605 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 90/189 367/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 87233435 m, 933982 m/sec, 87423975 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 95/189 386/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 91886413 m, 930595 m/sec, 92087418 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 100/189 406/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 96562656 m, 935248 m/sec, 96774206 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 105/189 425/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 101223041 m, 932077 m/sec, 101445141 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 110/189 445/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 105901128 m, 935617 m/sec, 106133853 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 115/189 465/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 110614087 m, 942591 m/sec, 110857547 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 120/189 484/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 115339116 m, 945005 m/sec, 115593371 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 125/189 504/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 120013935 m, 934963 m/sec, 120278910 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 130/189 523/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 124556863 m, 908585 m/sec, 124832283 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 135/189 542/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 129149761 m, 918579 m/sec, 129435771 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 140/189 562/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 133754887 m, 921025 m/sec, 134051547 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 145/189 581/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 138370023 m, 923027 m/sec, 138677388 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 19 CTL EXCL 150/189 601/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 143036667 m, 933328 m/sec, 143354882 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 19 CTL EXCL 155/189 620/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 147626100 m, 917886 m/sec, 147955020 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 160/189 639/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 152269380 m, 928656 m/sec, 152609165 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 165/189 659/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 156903502 m, 926824 m/sec, 157254152 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 170/189 678/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 161562771 m, 931853 m/sec, 161924380 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 175/189 698/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 166195880 m, 926621 m/sec, 166568420 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 180/189 717/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 170797439 m, 920311 m/sec, 171180859 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 185/189 736/2000 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06 175377255 m, 915963 m/sec, 175771531 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-11: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15: DISJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06
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[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-2023-15
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-03: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-09: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC05000vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC05000vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575300426"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC05000vN.tgz
mv TwoPhaseLocking-PT-nC05000vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;