About the Execution of LoLA for TwoPhaseLocking-PT-nC05000vD
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.743 | 637434.00 | 461722.00 | 2643.30 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575300418.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC05000vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575300418
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 440K
-rw-r--r-- 1 mcc users 7.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 72K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 19 07:39 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 19 19:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 10K Apr 13 07:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 95K Apr 13 07:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.7K Apr 13 07:08 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Apr 13 07:08 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-00
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-01
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-02
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-03
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-04
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-05
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-07
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-08
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-09
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-10
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-11
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-12
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-13
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-14
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717186688112
BK_STOP 1717187325546
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 144 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 55 (type EQUN) for 21 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 55 (type EQUN) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 5/211 6/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 1357796 m, 271559 m/sec, 4721518 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 10/211 12/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 2696765 m, 267793 m/sec, 9369509 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 15/211 17/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 3978858 m, 256418 m/sec, 13794512 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 20/211 22/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 5212858 m, 246800 m/sec, 18030333 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 25/211 27/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 6411451 m, 239718 m/sec, 22121590 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 30/211 32/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 7569393 m, 231588 m/sec, 26047390 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 35/211 37/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 8690631 m, 224247 m/sec, 29826728 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 75/211 71/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 16907650 m, 200657 m/sec, 57297719 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 85/211 77/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 18567877 m, 175980 m/sec, 64377562 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 90/211 81/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 19508550 m, 188134 m/sec, 67902738 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 95/211 85/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 20475664 m, 193422 m/sec, 71433826 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 100/211 89/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 21465970 m, 198061 m/sec, 74992795 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 105/211 93/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 22468866 m, 200579 m/sec, 78562582 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 115/211 101/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2024-06 24532008 m, 206377 m/sec, 85833698 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 2/217 7/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-15 1558499 m, 311699 m/sec, 3063684 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 12/217 29/2000 TwoPhaseLocking-PT-nC05000vD-CTLFireability-2023-15 6798343 m, 512328 m/sec, 13451682 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 405 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC05000vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC05000vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575300418"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC05000vD.tgz
mv TwoPhaseLocking-PT-nC05000vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;