About the Execution of LoLA for TwoPhaseLocking-PT-nC02000vN
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.947 | 434848.00 | 433034.00 | 1125.90 | ??F????????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575200410.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC02000vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575200410
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 448K
-rw-r--r-- 1 mcc users 8.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 91K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.7K Apr 13 07:05 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 66K Apr 13 07:05 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 13 07:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 109K Apr 13 07:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-00
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-01
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-02
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-03
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-04
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-06
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-07
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-08
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-09
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-10
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-12
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-13
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-14
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717186141384
FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717186576232
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5005
[[35mlola[0m][I] fired transitions : 12014
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 180 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 16 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 55 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-04: CONJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-08: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-13: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 5/180 6/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 1410093 m, 282018 m/sec, 5180847 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-04: CONJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-08: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-13: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 10/180 12/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 2723569 m, 262695 m/sec, 9864753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-01: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-04: CONJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-08: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-13: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 15/180 16/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 3893454 m, 233977 m/sec, 13902006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
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[[35mlola[0m][.] 28 CTL EXCL 20/180 21/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 5095246 m, 240358 m/sec, 17923139 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 25/180 26/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 6251085 m, 231167 m/sec, 21671922 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 30/180 30/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 7297614 m, 209305 m/sec, 25028475 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 35/180 35/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 8428200 m, 226117 m/sec, 28657576 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 40/180 40/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 9605173 m, 235394 m/sec, 32852719 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 45/180 45/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 10767442 m, 232453 m/sec, 37447219 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 55/180 54/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 12965973 m, 218928 m/sec, 46139437 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 60/180 58/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 14044073 m, 215620 m/sec, 50412280 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 65/180 62/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 15125187 m, 216222 m/sec, 54692932 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 70/180 67/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 16202608 m, 215484 m/sec, 58962834 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 75/180 71/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 17269971 m, 213472 m/sec, 63177876 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 80/180 76/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 18337683 m, 213542 m/sec, 67384094 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 85/180 80/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 19380495 m, 208562 m/sec, 71511007 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 100/180 93/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 22552028 m, 210619 m/sec, 84049812 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 110/180 101/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 24628265 m, 206265 m/sec, 92255535 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 115/180 105/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 25673150 m, 208977 m/sec, 96372073 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 120/180 110/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05 26717688 m, 208907 m/sec, 100475062 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-04: CONJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-13: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-05
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[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-04
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[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-12
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-13: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 50 CTL EXCL 5/227 19/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 4520191 m, 904038 m/sec, 4774189 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-13: CONJ 0 1 0 0 4 0 0 0
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[[35mlola[0m][.] 50 CTL EXCL 10/227 34/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 8103372 m, 716636 m/sec, 8575185 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC02000vN-CTLFireability-2023-13: CONJ 0 1 0 0 4 0 0 0
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[[35mlola[0m][.] 50 CTL EXCL 15/227 48/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 11520973 m, 683520 m/sec, 12151609 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 20/227 63/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 14892981 m, 674401 m/sec, 15661028 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 25/227 76/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 18165018 m, 654407 m/sec, 19055255 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 30/227 90/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 21455620 m, 658120 m/sec, 22459356 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 35/227 103/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 24661691 m, 641214 m/sec, 25768186 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 40/227 117/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 27966041 m, 660870 m/sec, 29173675 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 45/227 131/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 31184724 m, 643736 m/sec, 32487269 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 50/227 144/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 34342075 m, 631470 m/sec, 35734292 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 55/227 157/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 37518410 m, 635267 m/sec, 39000162 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 115/227 311/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 74058322 m, 575462 m/sec, 76402973 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 120/227 323/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 76927949 m, 573925 m/sec, 79333169 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 125/227 335/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 79815493 m, 577508 m/sec, 82281635 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 130/227 348/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 82909849 m, 618871 m/sec, 85438831 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 135/227 360/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 85873632 m, 592756 m/sec, 88464696 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 140/227 372/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 88787072 m, 582688 m/sec, 91435969 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 145/227 385/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 91781589 m, 598903 m/sec, 94488651 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 205/227 526/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 125466754 m, 572811 m/sec, 128803257 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 210/227 538/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 128348797 m, 576408 m/sec, 131736574 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 215/227 550/2000 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-11 131166123 m, 563465 m/sec, 134604193 t fired, .
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[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-09
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[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 36 TwoPhaseLocking-PT-nC02000vN-CTLFireability-2024-08
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 403 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC02000vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC02000vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575200410"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC02000vN.tgz
mv TwoPhaseLocking-PT-nC02000vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;