About the Execution of LoLA for TwoPhaseLocking-PT-nC01000vN
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16206.384 | 622125.00 | 616136.00 | 2386.50 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575200394.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC01000vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575200394
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 408K
-rw-r--r-- 1 mcc users 5.1K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 44K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 73K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.4K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 19 07:39 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 19:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.4K Apr 13 07:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 86K Apr 13 07:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.1K Apr 13 07:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K Apr 13 07:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-00
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-01
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-02
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-03
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-04
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-05
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-06
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-07
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-09
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-10
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-11
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-12
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-13
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-14
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717181413908
BK_STOP 1717182036033
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 3 (type EXCL) for 0 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 3 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 0 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type EQUN) for 11 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 80 (type EQUN) for 62 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 71 (type EQUN) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 77 (type EQUN) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 80 (type EQUN) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 126756
[[35mlola[0m][I] fired transitions : 255507
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 66 (type EXCL) for 65 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 66 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4009
[[35mlola[0m][I] fired transitions : 6015
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 59 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 126258
[[35mlola[0m][I] fired transitions : 127757
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1001
[[35mlola[0m][I] fired transitions : 1003
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7001
[[35mlola[0m][I] fired transitions : 9016
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1999
[[35mlola[0m][I] fired transitions : 3511
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 40 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-00: CONJ 0 2 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-01: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 5/257 9/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 2188811 m, 437762 m/sec, 5231913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-00: CONJ 0 2 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-01: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 10/257 19/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 4498875 m, 462012 m/sec, 10833919 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-00: CONJ 0 2 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-01: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 15/257 28/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 6642344 m, 428693 m/sec, 16053439 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC01000vN-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-00: CONJ 0 2 0 0 5 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-01: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 45 CTL EXCL 20/257 37/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 8785444 m, 428620 m/sec, 21283622 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 30/257 54/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 12945110 m, 414701 m/sec, 31446064 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 35/257 62/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 14976120 m, 406202 m/sec, 36417879 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 40/257 70/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 16930900 m, 390956 m/sec, 41212811 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 65/257 109/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 26420968 m, 368107 m/sec, 64494199 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 75/257 124/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 30167036 m, 369637 m/sec, 73687460 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 80/257 132/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 31999666 m, 366526 m/sec, 78190835 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 145/257 228/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 55467200 m, 357463 m/sec, 135927806 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 150/257 235/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 57201089 m, 346777 m/sec, 140201022 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 155/257 242/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 58912322 m, 342246 m/sec, 144419916 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 180/257 277/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 67502710 m, 335685 m/sec, 165581213 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 185/257 284/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 69198180 m, 339094 m/sec, 169760682 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 190/257 291/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 70882264 m, 336816 m/sec, 173912131 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 195/257 298/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 72548462 m, 333239 m/sec, 178019477 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 200/257 305/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-08 74234366 m, 337180 m/sec, 182175759 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 5/277 10/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-05 2382567 m, 476513 m/sec, 4999023 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 10/277 19/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-05 4613090 m, 446104 m/sec, 10136415 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 155/277 242/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-05 60043700 m, 351987 m/sec, 144486155 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 195/277 301/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-05 74612204 m, 372905 m/sec, 180103115 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 235/277 358/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-05 88989778 m, 350455 m/sec, 215485081 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 275/277 416/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-05 103439252 m, 348675 m/sec, 251048613 t fired, .
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[[35mlola[0m][.] 23 CTL EXCL 5/305 10/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-02 2410833 m, 482166 m/sec, 5055540 t fired, .
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[[35mlola[0m][.] 23 CTL EXCL 10/305 19/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-02 4659825 m, 449798 m/sec, 10252673 t fired, .
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[[35mlola[0m][.] 23 CTL EXCL 15/305 28/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-02 6806476 m, 429330 m/sec, 15307795 t fired, .
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[[35mlola[0m][.] 23 CTL EXCL 30/305 53/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-02 12983337 m, 404648 m/sec, 30026536 t fired, .
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[[35mlola[0m][.] 23 CTL EXCL 40/305 69/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-02 17044812 m, 413097 m/sec, 39665613 t fired, .
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[[35mlola[0m][.] 23 CTL EXCL 45/305 77/2000 TwoPhaseLocking-PT-nC01000vN-CTLFireability-2024-02 18965484 m, 384134 m/sec, 44456259 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC01000vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC01000vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575200394"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC01000vN.tgz
mv TwoPhaseLocking-PT-nC01000vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;