About the Execution of LoLA for TwoPhaseLocking-PT-nC00500vD
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16208.451 | 750765.00 | 724846.00 | 2886.20 | ???????FFT?????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575200370.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC00500vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575200370
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 544K
-rw-r--r-- 1 mcc users 9.5K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 99K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 65K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 13 06:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 140K Apr 13 06:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 13 06:52 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 105K Apr 13 06:52 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-01
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-02
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-03
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-04
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-05
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-06
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-07
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-08
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-09
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-10
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-11
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-12
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-14
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717175959467
FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717176710232
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 34 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 112 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 120 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1504
[[35mlola[0m][I] fired transitions : 4514
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1001
[[35mlola[0m][I] fired transitions : 1001
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 44 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 44 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1001
[[35mlola[0m][I] fired transitions : 1001
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 61 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-12
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 31875
[[35mlola[0m][I] fired transitions : 32872
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 50 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1011
[[35mlola[0m][I] fired transitions : 2014
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 50 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1000
[[35mlola[0m][I] fired transitions : 999
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 50 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 501
[[35mlola[0m][I] fired transitions : 501
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 300 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-14: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-05: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-10: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-12: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 5/300 5/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 1121763 m, 224352 m/sec, 4048625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-14: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-05: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-10: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-12: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 10/300 10/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 2248631 m, 225373 m/sec, 8174172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-14: CONJ true CONJ[0m
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[[35mlola[0m][.] 48 CTL EXCL 15/300 15/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 3383744 m, 227022 m/sec, 12338250 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 20/300 19/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 4496891 m, 222629 m/sec, 16419185 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 25/300 24/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 5592347 m, 219091 m/sec, 20434735 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 30/300 28/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 6671683 m, 215867 m/sec, 24392635 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 35/300 32/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 7700656 m, 205794 m/sec, 28166717 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 40/300 37/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 8761657 m, 212200 m/sec, 32057363 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 45/300 41/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 9817907 m, 211250 m/sec, 35931229 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 50/300 46/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 10874350 m, 211288 m/sec, 39806718 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 55/300 50/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 11959131 m, 216956 m/sec, 43844175 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 60/300 53/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 12818003 m, 171774 m/sec, 48121237 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 65/300 57/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 13681416 m, 172682 m/sec, 52422558 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 70/300 60/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 14585205 m, 180757 m/sec, 56922752 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 75/300 64/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13 15602693 m, 203497 m/sec, 61992091 t fired, .
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[[35mlola[0m][.] 23 CTL EXCL 4/320 11/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-06 2562733 m, 512546 m/sec, 5067448 t fired, .
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[[35mlola[0m][.] 23 CTL EXCL 9/320 22/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-06 5262122 m, 539877 m/sec, 10430874 t fired, .
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[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-05
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[[35mlola[0m][I] FINISHED task # 18 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-05
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[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2003
[[35mlola[0m][I] fired transitions : 7016
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-03
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[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 32879
[[35mlola[0m][I] fired transitions : 35378
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[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-01
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[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-01
[[35mlola[0m][I] result : false
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[[35mlola[0m][.] 1 CTL EXCL 3/702 6/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 1294484 m, 258896 m/sec, 3802695 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 8/702 11/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 2696980 m, 280499 m/sec, 8117138 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 13/702 16/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 3948613 m, 250326 m/sec, 12046465 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 18/702 21/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 5114057 m, 233088 m/sec, 15749610 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 23/702 26/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 6227863 m, 222761 m/sec, 19269454 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 28/702 30/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 7277105 m, 209848 m/sec, 22692513 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 33/702 34/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 8338904 m, 212359 m/sec, 26034077 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 38/702 38/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 9336320 m, 199483 m/sec, 29301637 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 43/702 42/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 10316017 m, 195939 m/sec, 32506222 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 48/702 46/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 11281706 m, 193137 m/sec, 35679641 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 53/702 50/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 12195686 m, 182796 m/sec, 38762522 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 58/702 53/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 13137772 m, 188417 m/sec, 41820908 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 63/702 57/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 14047778 m, 182001 m/sec, 44863617 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 68/702 61/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 14978802 m, 186204 m/sec, 47892845 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 73/702 64/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 15881539 m, 180547 m/sec, 50840838 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 78/702 68/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 16744143 m, 172520 m/sec, 53776385 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 83/702 71/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 17625827 m, 176336 m/sec, 56695754 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 88/702 75/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 18452747 m, 165384 m/sec, 59529333 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 93/702 78/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 19299992 m, 169449 m/sec, 62398704 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 98/702 81/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 20134795 m, 166960 m/sec, 65204871 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 103/702 85/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 21018329 m, 176706 m/sec, 68043378 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 108/702 88/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 21847778 m, 165889 m/sec, 70749250 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 113/702 91/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 22652512 m, 160946 m/sec, 73545494 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 118/702 95/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 23473166 m, 164130 m/sec, 76320812 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 123/702 98/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 24303532 m, 166073 m/sec, 79124227 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 128/702 101/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 25111717 m, 161637 m/sec, 81760827 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 133/702 104/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 25885476 m, 154751 m/sec, 84428220 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 138/702 108/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 26681639 m, 159232 m/sec, 87181445 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 143/702 111/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 27463196 m, 156311 m/sec, 89834882 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 148/702 114/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 28260449 m, 159450 m/sec, 92537829 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 153/702 117/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 29038447 m, 155599 m/sec, 95177350 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 158/702 120/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 29828598 m, 158030 m/sec, 97867809 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 163/702 124/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 30630556 m, 160391 m/sec, 100497220 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 168/702 127/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 31386129 m, 151114 m/sec, 103090051 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 173/702 130/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 32225209 m, 167816 m/sec, 105812820 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 178/702 133/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 32981223 m, 151202 m/sec, 108384171 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 183/702 136/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 33745129 m, 152781 m/sec, 110954522 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 188/702 139/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 34486863 m, 148346 m/sec, 113560139 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 193/702 142/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 35289069 m, 160441 m/sec, 116142570 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 198/702 145/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 36025716 m, 147329 m/sec, 118685706 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 203/702 148/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 36759189 m, 146694 m/sec, 121239064 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 208/702 151/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 37523258 m, 152813 m/sec, 123770092 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 213/702 154/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 38257217 m, 146791 m/sec, 126315859 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 218/702 157/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 39008611 m, 150278 m/sec, 128893050 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 223/702 160/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 39768062 m, 151890 m/sec, 131392340 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 228/702 163/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 40485437 m, 143475 m/sec, 133881275 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 233/702 166/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 41223794 m, 147671 m/sec, 136346931 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 238/702 169/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 41939443 m, 143129 m/sec, 138853015 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 243/702 172/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 42696770 m, 151465 m/sec, 141328404 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 248/702 175/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 43426248 m, 145895 m/sec, 143784726 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 253/702 178/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 44142103 m, 143171 m/sec, 146293085 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 258/702 181/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 44899317 m, 151442 m/sec, 148752247 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 263/702 184/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 45642520 m, 148640 m/sec, 151219460 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 273/702 189/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 47071926 m, 145014 m/sec, 156156169 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 278/702 192/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 47798102 m, 145235 m/sec, 158597356 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 283/702 195/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 48535624 m, 147504 m/sec, 161045319 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 288/702 198/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 49274493 m, 147773 m/sec, 163513524 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 293/702 201/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 49963871 m, 137875 m/sec, 165948164 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 298/702 204/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 50669329 m, 141091 m/sec, 168343831 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 303/702 207/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 51409979 m, 148130 m/sec, 170762717 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 308/702 210/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 52114102 m, 140824 m/sec, 173171894 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 313/702 213/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 52830779 m, 143335 m/sec, 175648063 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 318/702 215/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 53515579 m, 136960 m/sec, 178011906 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 323/702 218/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 54218886 m, 140661 m/sec, 180331838 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 328/702 221/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 54911878 m, 138598 m/sec, 182739361 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 333/702 224/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 55583228 m, 134270 m/sec, 185041512 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 338/702 226/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 56286553 m, 140665 m/sec, 187408955 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 343/702 229/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 56989205 m, 140530 m/sec, 189726715 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 348/702 232/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 57668949 m, 135948 m/sec, 192129630 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 353/702 235/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 58379231 m, 142056 m/sec, 194506134 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 358/702 238/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 59100641 m, 144282 m/sec, 196889161 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 363/702 240/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 59773553 m, 134582 m/sec, 199317519 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 368/702 243/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 60446872 m, 134663 m/sec, 201644398 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 373/702 246/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 61122938 m, 135213 m/sec, 203967600 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 378/702 249/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 61838200 m, 143052 m/sec, 206318351 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 383/702 251/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 62529141 m, 138188 m/sec, 208655697 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 388/702 254/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 63194343 m, 133040 m/sec, 211066195 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 393/702 257/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 63875980 m, 136327 m/sec, 213395745 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 398/702 260/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 64543528 m, 133509 m/sec, 215693222 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 403/702 262/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 65220218 m, 135338 m/sec, 218114343 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 408/702 265/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 65920248 m, 140006 m/sec, 220449710 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 413/702 268/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 66621402 m, 140230 m/sec, 222785170 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 418/702 271/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 67324747 m, 140669 m/sec, 225113571 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 423/702 273/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 67997336 m, 134517 m/sec, 227408700 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 428/702 276/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 68655369 m, 131606 m/sec, 229813244 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 433/702 279/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 69353634 m, 139653 m/sec, 232128821 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 438/702 282/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 70019931 m, 133259 m/sec, 234425541 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 443/702 284/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 70718548 m, 139723 m/sec, 236726301 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 448/702 287/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 71374102 m, 131110 m/sec, 238997438 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 453/702 290/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 72053964 m, 135972 m/sec, 241317701 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 458/702 292/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 72737410 m, 136689 m/sec, 243718689 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 463/702 295/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 73398924 m, 132302 m/sec, 245973244 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 468/702 298/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 74080018 m, 136218 m/sec, 248261762 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 473/702 301/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 74744038 m, 132804 m/sec, 250545014 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 478/702 303/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 75399501 m, 131092 m/sec, 252811538 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 483/702 306/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 76062500 m, 132599 m/sec, 255209712 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 488/702 308/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 76720446 m, 131589 m/sec, 257476757 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 493/702 311/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 77365061 m, 128923 m/sec, 259707228 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 498/702 314/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 78061577 m, 139303 m/sec, 262004945 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 503/702 316/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 78728837 m, 133452 m/sec, 264276107 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 508/702 319/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 79384248 m, 131082 m/sec, 266535499 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 513/702 322/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 80055303 m, 134211 m/sec, 268812043 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 518/702 325/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 80732830 m, 135505 m/sec, 271205791 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 523/702 327/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 81417034 m, 136840 m/sec, 273483038 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 528/702 330/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 82064544 m, 129502 m/sec, 275719881 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 533/702 333/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 82751539 m, 137399 m/sec, 277977411 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 538/702 335/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 83379110 m, 125514 m/sec, 280168010 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 543/702 338/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 84027579 m, 129693 m/sec, 282403668 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 548/702 340/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 84682513 m, 130986 m/sec, 284746136 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 553/702 343/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 85334820 m, 130461 m/sec, 286988386 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 558/702 346/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 85999938 m, 133023 m/sec, 289217978 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 563/702 348/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 86677271 m, 135466 m/sec, 291454945 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 568/702 351/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 87298060 m, 124157 m/sec, 293611019 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 573/702 354/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 87967218 m, 133831 m/sec, 295848011 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 578/702 356/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 88606653 m, 127887 m/sec, 298056979 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 583/702 359/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 89283010 m, 135271 m/sec, 300468189 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 588/702 361/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 89922970 m, 127992 m/sec, 302713150 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 593/702 364/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 90563788 m, 128163 m/sec, 304915906 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 598/702 367/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 91232133 m, 133669 m/sec, 307139571 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 603/702 369/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 91863651 m, 126303 m/sec, 309330038 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 608/702 372/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 92511888 m, 129647 m/sec, 311528914 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 613/702 374/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 93171317 m, 131885 m/sec, 313745244 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 618/702 377/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 93822942 m, 130325 m/sec, 315943518 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 623/702 379/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 94328451 m, 101101 m/sec, 317787472 t fired, .
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[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-14: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-10: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00500vD-CTLFireability-2023-12: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 658/702 380/2000 TwoPhaseLocking-PT-nC00500vD-CTLFireability-2024-00 94643969 m, 63103 m/sec, 318885295 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00500vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC00500vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575200370"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00500vD.tgz
mv TwoPhaseLocking-PT-nC00500vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;