About the Execution of LoLA for TwoPhaseLocking-PT-nC00200vN
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.735 | 598429.00 | 595718.00 | 2333.60 | T??????????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575100362.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC00200vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575100362
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 428K
-rw-r--r-- 1 mcc users 8.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.6K Apr 13 07:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 89K Apr 13 07:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Apr 13 07:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Apr 13 07:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14
FORMULA_NAME TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717174750157
FORMULA TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717175348586
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 0 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 52 (type EQUN) for 0 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 49 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 402
[[35mlola[0m][I] fired transitions : 401
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 52 (type EQUN) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type EQUN) for 12 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type EQUN) for 12 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN) for 30 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type EQUN) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 69 (type EQUN) for 30 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type EQUN) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 52 (type EQUN) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 58 (type EQUN) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 69 (type EQUN) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00: AXAF true state space /EXEG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/240 10/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 2378492 m, 475698 m/sec, 5668029 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00: AXAF true state space /EXEG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/240 19/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 4488353 m, 421972 m/sec, 10799548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00: AXAF true state space /EXEG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 15/240 27/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 6625283 m, 427386 m/sec, 16020814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00: AXAF true state space /EXEG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 20/240 36/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 8795465 m, 434036 m/sec, 21321946 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00: AXAF true state space /EXEG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 25/240 45/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 11053653 m, 451637 m/sec, 26845080 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-00: AXAF true state space /EXEG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 30/240 53/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 13181819 m, 425633 m/sec, 32054041 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 35/240 62/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 15374643 m, 438564 m/sec, 37410169 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 40/240 71/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 17673123 m, 459696 m/sec, 42973090 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 45/240 76/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 18776482 m, 220671 m/sec, 48575051 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 50/240 80/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 19785373 m, 201778 m/sec, 53833542 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 55/240 84/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 20769881 m, 196901 m/sec, 58864540 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 60/240 88/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 21725341 m, 191092 m/sec, 63712616 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 65/240 91/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 22682844 m, 191500 m/sec, 68533534 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 70/240 95/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 23633444 m, 190120 m/sec, 73272212 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 4 CTL EXCL 75/240 99/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 24580372 m, 189385 m/sec, 78007127 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 80/240 103/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 25517147 m, 187355 m/sec, 82651753 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 85/240 107/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 26450954 m, 186761 m/sec, 87269118 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 90/240 110/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 27379551 m, 185719 m/sec, 91859924 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 95/240 114/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 28299910 m, 184071 m/sec, 96395536 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 100/240 118/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 29219885 m, 183995 m/sec, 100932591 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 105/240 121/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 30131514 m, 182325 m/sec, 105417169 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 110/240 125/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 31043582 m, 182413 m/sec, 109893954 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 115/240 129/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 31941729 m, 179629 m/sec, 114288292 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 120/240 132/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 32836926 m, 179039 m/sec, 118677859 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 125/240 136/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 33732302 m, 179075 m/sec, 123060918 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 130/240 139/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 34630116 m, 179562 m/sec, 127447520 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 135/240 143/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 35517695 m, 177515 m/sec, 131786738 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 140/240 147/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 36411516 m, 178764 m/sec, 136132500 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 145/240 150/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 37294190 m, 176534 m/sec, 140420075 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 150/240 154/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 38174505 m, 176063 m/sec, 144730011 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 155/240 157/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 39059657 m, 177030 m/sec, 149027936 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 160/240 161/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 39946809 m, 177430 m/sec, 153366051 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 165/240 164/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 40826821 m, 176002 m/sec, 157654703 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 170/240 168/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 41714993 m, 177634 m/sec, 161939804 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 175/240 171/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 42593927 m, 175786 m/sec, 166240824 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 180/240 175/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 43474625 m, 176139 m/sec, 170507622 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 185/240 178/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 44347077 m, 174490 m/sec, 174770862 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 190/240 182/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 45230051 m, 176594 m/sec, 179035878 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 195/240 185/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 46108855 m, 175760 m/sec, 183294515 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 200/240 189/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 46974513 m, 173131 m/sec, 187509483 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 205/240 192/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 47848002 m, 174697 m/sec, 191737473 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 210/240 196/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 48718764 m, 174152 m/sec, 195930690 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 215/240 199/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 49584249 m, 173097 m/sec, 200155574 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 220/240 203/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 50457162 m, 174582 m/sec, 204368081 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 4 CTL EXCL 225/240 206/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 51319067 m, 172381 m/sec, 208563184 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 4 CTL EXCL 230/240 210/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 52183049 m, 172796 m/sec, 212722955 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 235/240 213/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 53043465 m, 172083 m/sec, 216894271 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 240/240 217/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01 53896073 m, 170521 m/sec, 220997401 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 239 sec
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[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 3355 sec
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[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 403
[[35mlola[0m][I] fired transitions : 405
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[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-15: CTL false CTL model checker[0m
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 257 sec
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[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 697201
[[35mlola[0m][I] fired transitions : 2783451
[[35mlola[0m][I] time used : 1
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[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 279 sec
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[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 201
[[35mlola[0m][I] fired transitions : 201
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 304 sec
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[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-11: CTL true CTL model checker[0m
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 28 CTL EXCL 4/304 8/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 1825800 m, 365160 m/sec, 4331586 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 28 CTL EXCL 9/304 18/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 4237524 m, 482344 m/sec, 10189640 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 28 CTL EXCL 14/304 27/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 6604758 m, 473446 m/sec, 15970140 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-05: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-07: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 28 CTL EXCL 19/304 37/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 8983464 m, 475741 m/sec, 21780784 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 28 CTL EXCL 24/304 46/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 11359106 m, 475128 m/sec, 27592930 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 28 CTL EXCL 29/304 56/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 13736514 m, 475481 m/sec, 33407849 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 28 CTL EXCL 34/304 65/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 16186913 m, 490079 m/sec, 39390414 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 28 CTL EXCL 39/304 74/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 18217409 m, 406099 m/sec, 45254736 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 44/304 78/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 19381502 m, 232818 m/sec, 49956216 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 49/304 83/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 20467271 m, 217153 m/sec, 54235692 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 28 CTL EXCL 54/304 87/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 21537029 m, 213951 m/sec, 58378454 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-10: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 28 CTL EXCL 59/304 91/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 22586995 m, 209993 m/sec, 62423892 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 64/304 95/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 23626034 m, 207807 m/sec, 66390245 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 69/304 99/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 24650968 m, 204986 m/sec, 70314129 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 74/304 103/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 25673555 m, 204517 m/sec, 74193053 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 79/304 108/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 26689244 m, 203137 m/sec, 78051552 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 84/304 112/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 27699249 m, 202001 m/sec, 81870327 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 89/304 116/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 28704987 m, 201147 m/sec, 85683147 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 94/304 120/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 29708407 m, 200684 m/sec, 89472837 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 99/304 124/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 30710797 m, 200478 m/sec, 93244312 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 104/304 128/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 31709254 m, 199691 m/sec, 96995759 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 109/304 132/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 32694024 m, 196954 m/sec, 100709597 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 114/304 136/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 33679124 m, 197020 m/sec, 104405258 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 119/304 140/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 34662128 m, 196600 m/sec, 108098257 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 124/304 143/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 35636822 m, 194938 m/sec, 111755661 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 129/304 147/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 36616664 m, 195968 m/sec, 115408772 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 134/304 151/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 37585260 m, 193719 m/sec, 119050974 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 139/304 155/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 38556949 m, 194337 m/sec, 122675446 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 144/304 159/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 39518442 m, 192298 m/sec, 126280499 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 149/304 163/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 40480637 m, 192439 m/sec, 129895985 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 154/304 167/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 41466775 m, 197227 m/sec, 133566791 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 159/304 171/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 42438127 m, 194270 m/sec, 137212885 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 164/304 175/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 43411369 m, 194648 m/sec, 140833239 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 169/304 179/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 44376356 m, 192997 m/sec, 144455281 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 174/304 182/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 45347811 m, 194291 m/sec, 148060582 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 179/304 186/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 46315437 m, 193525 m/sec, 151679622 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 184/304 190/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 47272621 m, 191436 m/sec, 155248971 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 189/304 194/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 48219764 m, 189428 m/sec, 158769120 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 194/304 198/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 49169387 m, 189924 m/sec, 162318102 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 199/304 202/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 50124528 m, 191028 m/sec, 165875331 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 204/304 205/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 51076499 m, 190394 m/sec, 169437248 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 209/304 209/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 52025591 m, 189818 m/sec, 172957443 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 214/304 213/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 52978460 m, 190573 m/sec, 176493762 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 219/304 217/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 53945676 m, 193443 m/sec, 180084982 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 28 CTL EXCL 224/304 221/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 54907389 m, 192342 m/sec, 183683574 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 229/304 225/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 55881224 m, 194767 m/sec, 187292999 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 234/304 229/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 56843929 m, 192541 m/sec, 190879273 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 239/304 232/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 57817613 m, 194736 m/sec, 194490137 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 244/304 236/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 58789464 m, 194370 m/sec, 198095410 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 249/304 240/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 59760324 m, 194172 m/sec, 201732207 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 254/304 244/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 60723994 m, 192734 m/sec, 205302218 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 259/304 248/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 61688256 m, 192852 m/sec, 208854844 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 264/304 252/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 62644816 m, 191312 m/sec, 212429972 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 269/304 256/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 63591152 m, 189267 m/sec, 215938907 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 274/304 259/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 64530853 m, 187940 m/sec, 219420554 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 279/304 263/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 65417945 m, 177418 m/sec, 222713742 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 284/304 267/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 66313431 m, 179097 m/sec, 226032957 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 289/304 270/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 67230922 m, 183498 m/sec, 229415096 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 294/304 274/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 68160594 m, 185934 m/sec, 232851840 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 299/304 278/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 69088765 m, 185634 m/sec, 236283242 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00200vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 28 CTL EXCL 304/304 281/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-09 70016198 m, 185486 m/sec, 239736850 t fired, .
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[[35mlola[0m][.] 25 CTL EXCL 5/304 12/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08 2793152 m, 558630 m/sec, 5911482 t fired, .
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[[35mlola[0m][.] 25 CTL EXCL 10/304 22/2000 TwoPhaseLocking-PT-nC00200vN-CTLFireability-2024-08 5312135 m, 503796 m/sec, 11241570 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 404 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00200vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC00200vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575100362"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00200vN.tgz
mv TwoPhaseLocking-PT-nC00200vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;