About the Execution of LoLA for TwoPhaseLocking-PT-nC00100vN
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3956.115 | 549749.00 | 555630.00 | 1292.00 | TTFFFFTFTTFFFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575100346.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC00100vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575100346
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 444K
-rw-r--r-- 1 mcc users 7.6K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 34K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 13 07:00 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Apr 13 07:00 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Apr 13 07:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 75K Apr 13 07:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-01
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-03
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-07
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-08
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-09
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-12
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-14
FORMULA_NAME TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717174066336
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00: CONJ true CONJ[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04: DISJ false DISJ[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10: EFAG false tscc_search[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11: EFEG false state space /EFEG[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 549 secs. Pages in use: 41
BK_STOP 1717174616085
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 69 (type EXCL) for 0 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 105 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 0 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type EQUN) for 16 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3976
[[35mlola[0m][I] fired transitions : 6474
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 72 (type EQUN) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][I] LAUNCH task # 74 (type EXCL) for 16 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 109 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 74 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 77 (type EQUN) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04 (obsolete)
[[35mlola[0m][I] LAUNCH task # 80 (type EXCL) for 0 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 78 (type FNDP) for 0 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 79 (type EQUN) for 0 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 80 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 78 (type FNDP) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][W] CANCELED task # 79 (type EQUN) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][I] FINISHED task # 78 (type FNDP) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 16 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 27 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 205
[[35mlola[0m][I] fired transitions : 461
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 7 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 150 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 77 (type EQUN) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 85 (type EQUN) for 50 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 87 (type EQUN) for 50 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 79 (type EQUN) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 85 (type EQUN) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 91 (type EQUN) for 53 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 93 (type EQUN) for 53 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 87 (type EQUN) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 91 (type EQUN) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 93 (type EQUN) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1216549
[[35mlola[0m][I] fired transitions : 2941926
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 5
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 56 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-00: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04: DISJ 0 3 0 0 8 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 57 CTL EXCL 3/224 5/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-12 1235531 m, 247106 m/sec, 3584156 t fired, .
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 135251
[[35mlola[0m][I] fired transitions : 529225
[[35mlola[0m][I] time used : 1
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[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 250 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 365
[[35mlola[0m][I] fired transitions : 569
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 270 sec
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 0/270 1/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 19156 m, 3831 m/sec, 62060 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04: DISJ 0 3 0 0 8 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 5/270 6/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 1392969 m, 274762 m/sec, 5917004 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04: DISJ 0 3 0 0 8 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 10/270 11/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 2592061 m, 239818 m/sec, 12723222 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04: DISJ 0 3 0 0 8 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 15/270 15/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 3684670 m, 218521 m/sec, 18948373 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-11: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 39 CTL EXCL 20/270 20/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 4758836 m, 214833 m/sec, 25301462 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-10: EFAG 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 39 CTL EXCL 25/270 24/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 5828206 m, 213874 m/sec, 31297201 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 30/270 28/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 6825904 m, 199539 m/sec, 37116753 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 35/270 32/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 7899146 m, 214648 m/sec, 43136069 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 40/270 36/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 8878361 m, 195843 m/sec, 49093895 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 45/270 40/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 9814226 m, 187173 m/sec, 55038278 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 50/270 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 9991962 m, 35547 m/sec, 60912307 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 55/270 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 10041809 m, 9969 m/sec, 66359993 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 60/270 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 10088183 m, 9274 m/sec, 71657327 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 75/270 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 10114058 m, 611 m/sec, 87113285 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 80/270 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 10115970 m, 382 m/sec, 92189722 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 90/270 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 10118977 m, 317 m/sec, 102169161 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 95/270 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 10119735 m, 151 m/sec, 107100127 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 120/270 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 10119973 m, 0 m/sec, 125705215 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 125/270 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 10119975 m, 0 m/sec, 129338960 t fired, .
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[[35mlola[0m][.] 39 CTL EXCL 130/270 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-06 10119981 m, 1 m/sec, 133403333 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 4/281 4/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 816314 m, 163262 m/sec, 4599281 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 9/281 7/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 1628939 m, 162525 m/sec, 9788607 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 14/281 10/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 2351733 m, 144558 m/sec, 14757515 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 19/281 13/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 3047052 m, 139063 m/sec, 19587216 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 24/281 15/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 3725797 m, 135749 m/sec, 24313127 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 34/281 20/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 4968074 m, 120237 m/sec, 33507384 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 39/281 23/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 5561292 m, 118643 m/sec, 37985266 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 44/281 25/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 6117812 m, 111304 m/sec, 42416618 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 49/281 27/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 6638633 m, 104164 m/sec, 46822097 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 69/281 35/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 8478162 m, 83465 m/sec, 64251913 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 74/281 36/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 8835629 m, 71493 m/sec, 68598782 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 79/281 37/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 9180676 m, 69009 m/sec, 72924233 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 84/281 38/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 9468468 m, 57558 m/sec, 77266130 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 89/281 39/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 9693505 m, 45007 m/sec, 81617872 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 104/281 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 10119953 m, 15844 m/sec, 95049236 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 109/281 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 10119966 m, 2 m/sec, 98308082 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 114/281 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 10119971 m, 1 m/sec, 101541704 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 119/281 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 10119974 m, 0 m/sec, 104846679 t fired, .
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[[35mlola[0m][.] 36 CTL EXCL 124/281 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-05 10119974 m, 0 m/sec, 108232491 t fired, .
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[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-08
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[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-03
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[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 62 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-14
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[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5300
[[35mlola[0m][I] fired transitions : 6528
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[[35mlola[0m][I] LAUNCH task # 21 (type EXCL) for 16 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04
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[[35mlola[0m][I] FINISHED task # 21 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1433
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[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 59 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13
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[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 91051
[[35mlola[0m][I] fired transitions : 400861
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 66 (type EXCL) for 65 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 1621 sec
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[[35mlola[0m][.] 66 CTL EXCL 2/1621 2/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 466616 m, 93323 m/sec, 2682773 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 7/1621 6/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 1455942 m, 197865 m/sec, 8641060 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 66 CTL EXCL 12/1621 10/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 2358547 m, 180521 m/sec, 14152988 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 17/1621 13/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 3182318 m, 164754 m/sec, 19220219 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 22/1621 17/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 3994524 m, 162441 m/sec, 24240098 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 27/1621 20/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 4789451 m, 158985 m/sec, 29171994 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 32/1621 23/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 5585317 m, 159173 m/sec, 34116381 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 37/1621 26/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 6376570 m, 158250 m/sec, 39045018 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 42/1621 29/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 7132551 m, 151196 m/sec, 43758986 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 47/1621 32/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 7874846 m, 148459 m/sec, 48384846 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 52/1621 35/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 8600859 m, 145202 m/sec, 52905989 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 57/1621 38/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 9315849 m, 142998 m/sec, 57345624 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 62/1621 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 10035549 m, 143940 m/sec, 61743572 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 67/1621 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 10112006 m, 15291 m/sec, 65258591 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 72/1621 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 10115559 m, 710 m/sec, 68579801 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 77/1621 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 10117642 m, 416 m/sec, 71935116 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 82/1621 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 10118855 m, 242 m/sec, 75265521 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 87/1621 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 10119631 m, 155 m/sec, 78512340 t fired, .
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[[35mlola[0m][.] 66 CTL EXCL 92/1621 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2023-15 10119938 m, 61 m/sec, 82089829 t fired, .
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[[35mlola[0m][I] result : true
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[[35mlola[0m][.] 11 CTL EXCL 1/3146 2/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 439913 m, 87982 m/sec, 1593587 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 6/3146 7/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 1646951 m, 241407 m/sec, 6517092 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 11/3146 11/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 2673776 m, 205365 m/sec, 10928821 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 16/3146 15/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 3636728 m, 192590 m/sec, 15132950 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 21/3146 19/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 4565651 m, 185784 m/sec, 19233473 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 26/3146 22/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 5457600 m, 178389 m/sec, 23246067 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 31/3146 26/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 6292899 m, 167059 m/sec, 27319886 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 36/3146 29/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 7078010 m, 157022 m/sec, 31372934 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 41/3146 32/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 7828956 m, 150189 m/sec, 35376120 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 46/3146 35/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 8474836 m, 129176 m/sec, 39357465 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 51/3146 37/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 9064196 m, 117872 m/sec, 43377102 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 56/3146 39/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 9557339 m, 98628 m/sec, 47467423 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 61/3146 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 10031729 m, 94878 m/sec, 51756386 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 66/3146 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 10112532 m, 16160 m/sec, 55269197 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 71/3146 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 10115824 m, 658 m/sec, 58504147 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 76/3146 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 10117681 m, 371 m/sec, 61750151 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 81/3146 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 10118899 m, 243 m/sec, 65047792 t fired, .
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[[35mlola[0m][.] 11 CTL EXCL 86/3146 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 10119630 m, 146 m/sec, 68338867 t fired, .
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[[35mlola[0m][.]
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 CTL EXCL 91/3146 41/2000 TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02 10119945 m, 63 m/sec, 71820076 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for TwoPhaseLocking-PT-nC00100vN-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 10119981
[[35mlola[0m][I] fired transitions : 75068466
[[35mlola[0m][I] time used : 95
[[35mlola[0m][I] memory pages used : 41
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00100vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC00100vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575100346"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00100vN.tgz
mv TwoPhaseLocking-PT-nC00100vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;