Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575100339.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC00100vD, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575100339
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 472K
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 68K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 13 07:15 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 149K Apr 13 07:15 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Apr 13 07:15 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K Apr 13 07:15 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1717173672230

FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL true LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F false state space / EG
[lola] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ false LTL model checker
[lola]
[lola] Time elapsed: 79 secs. Pages in use: 81

BK_STOP 1717173751227

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLCardinality.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 24 (type CNST) for 21 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 37 (type EXCL) for 32 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08
[lola][I] time limit : 112 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 24 (type CNST) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07
[lola][I] result : false
[lola][I] FINISHED task # 37 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02
[lola][I] time limit : 133 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02
[lola][I] result : false
[lola][I] markings : 251
[lola][I] fired transitions : 251
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 49 (type EXCL) for 48 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12
[lola][I] time limit : 144 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 49 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12
[lola][I] result : false
[lola][I] markings : 201
[lola][I] fired transitions : 201
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05
[lola][I] time limit : 211 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 69 (type FNDP) for 32 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 70 (type EQUN) for 32 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 16 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05
[lola][I] result : false
[lola][I] markings : 201
[lola][I] fired transitions : 201
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 43 (type EXCL) for 42 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10
[lola][I] time limit : 225 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 76 (type EQUN) for 58 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 43 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 54 (type EXCL) for 51 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13
[lola][I] time limit : 240 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 54 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13
[lola][I] result : false
[lola][I] markings : 201
[lola][I] fired transitions : 201
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 46 (type EXCL) for 45 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11
[lola][I] time limit : 300 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 46 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11
[lola][I] result : false
[lola][I] markings : 1321
[lola][I] fired transitions : 2142
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 40 (type EXCL) for 39 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09
[lola][I] time limit : 360 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 69 (type FNDP) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 1
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 70 (type EQUN) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08 (obsolete)
[lola][I] FINISHED task # 70 (type EQUN) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08
[lola][I] result : true
[lola][I] FINISHED task # 76 (type EQUN) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 5/400 11/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 1632638 m, 326527 m/sec, 4984270 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 11
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 10/400 20/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 3078005 m, 289073 m/sec, 9538850 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 20
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 15/400 29/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 4432513 m, 270901 m/sec, 13763996 t fired, .
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 29
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 20/400 38/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 5767660 m, 267029 m/sec, 17889852 t fired, .
[lola][.]
[lola][.] Time elapsed: 20 secs. Pages in use: 38
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 25/400 46/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 7093832 m, 265234 m/sec, 21927221 t fired, .
[lola][.]
[lola][.] Time elapsed: 25 secs. Pages in use: 46
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 30/400 55/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 8436896 m, 268612 m/sec, 26127497 t fired, .
[lola][.]
[lola][.] Time elapsed: 30 secs. Pages in use: 55
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 35/400 63/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 9779964 m, 268613 m/sec, 30194585 t fired, .
[lola][.]
[lola][.] Time elapsed: 35 secs. Pages in use: 63
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 40/400 72/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 11121800 m, 268367 m/sec, 34238659 t fired, .
[lola][.]
[lola][.] Time elapsed: 40 secs. Pages in use: 72
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 45/400 80/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 12340557 m, 243751 m/sec, 38576278 t fired, .
[lola][.]
[lola][.] Time elapsed: 45 secs. Pages in use: 80
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 50/400 80/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 12422149 m, 16318 m/sec, 42619096 t fired, .
[lola][.]
[lola][.] Time elapsed: 50 secs. Pages in use: 80
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 55/400 80/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 12474385 m, 10447 m/sec, 46447413 t fired, .
[lola][.]
[lola][.] Time elapsed: 55 secs. Pages in use: 80
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 60/400 81/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 12511654 m, 7453 m/sec, 50193715 t fired, .
[lola][.]
[lola][.] Time elapsed: 60 secs. Pages in use: 81
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 65/400 81/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 12537738 m, 5216 m/sec, 53941469 t fired, .
[lola][.]
[lola][.] Time elapsed: 65 secs. Pages in use: 81
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 70/400 81/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 12555461 m, 3544 m/sec, 57773473 t fired, .
[lola][.]
[lola][.] Time elapsed: 70 secs. Pages in use: 81
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-02: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-05: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-07: CONJ false preprocessing
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-08: CONJ false findpath
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-10: LTL true LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-11: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-12: LTL false LTL model checker
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-13: CONJ false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14: F 0 1 0 0 2 0 0 0
[lola][.] TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15: CONJ 0 2 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 75/400 81/2000 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09 12563123 m, 1532 m/sec, 61811215 t fired, .
[lola][.]
[lola][.] Time elapsed: 75 secs. Pages in use: 81
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 40 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-09
[lola][I] result : true
[lola][I] markings : 12564403
[lola][I] fired transitions : 64856091
[lola][I] time used : 79
[lola][I] memory pages used : 81
[lola][I] LAUNCH task # 66 (type EXCL) for 61 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15
[lola][I] time limit : 440 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 66 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 64 (type EXCL) for 61 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15
[lola][I] time limit : 503 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 64 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-15
[lola][I] result : false
[lola][I] markings : 201
[lola][I] fired transitions : 201
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04
[lola][I] time limit : 586 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-04
[lola][I] result : false
[lola][I] markings : 201
[lola][I] fired transitions : 201
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01
[lola][I] time limit : 704 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-01
[lola][I] result : false
[lola][I] markings : 204
[lola][I] fired transitions : 204
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00
[lola][I] time limit : 880 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-00
[lola][I] result : false
[lola][I] markings : 1056
[lola][I] fired transitions : 1527
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 73 (type EXCL) for 58 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14
[lola][I] time limit : 1173 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 73 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-14
[lola][I] result : true
[lola][I] markings : 101
[lola][I] fired transitions : 101
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03
[lola][I] time limit : 1760 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-03
[lola][I] result : false
[lola][I] markings : 351
[lola][I] fired transitions : 452
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06
[lola][I] time limit : 3521 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-LTLCardinality-06
[lola][I] result : false
[lola][I] markings : 533
[lola][I] fired transitions : 860
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00100vD"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC00100vD, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575100339"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00100vD.tgz
mv TwoPhaseLocking-PT-nC00100vD execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;