About the Execution of LoLA for TwoPhaseLocking-PT-nC00100vD
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6949.819 | 520511.00 | 524316.00 | 1371.10 | TTFFFTTTTFTFTTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575100338.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC00100vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575100338
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 472K
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 68K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 13 07:15 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 149K Apr 13 07:15 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Apr 13 07:15 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K Apr 13 07:15 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-02
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-03
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-04
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-05
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-06
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-07
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-08
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-09
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-11
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-14
FORMULA_NAME TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717173546792
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-06: SP ACTL true LTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15: CONJ false CONJ[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 520 secs. Pages in use: 40
BK_STOP 1717174067303
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 45 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 101
[[35mlola[0m][I] fired transitions : 303
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 5/224 10/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 2362291 m, 472458 m/sec, 4755034 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 10/224 17/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 4029132 m, 333368 m/sec, 9683395 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 15/224 22/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 5317941 m, 257761 m/sec, 14553519 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15: CONJ 0 2 0 0 4 0 0 0
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[[35mlola[0m][.] 37 CTL EXCL 25/224 29/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 7024929 m, 150879 m/sec, 24297146 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 30/224 31/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 7595100 m, 114034 m/sec, 28736822 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 35/224 33/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 8110418 m, 103063 m/sec, 33465755 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 65/224 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 9727353 m, 29209 m/sec, 61750564 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 75/224 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 9803022 m, 64 m/sec, 69412337 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 80/224 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 9803261 m, 47 m/sec, 72665609 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 85/224 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 9803461 m, 40 m/sec, 75976215 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 90/224 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 9803620 m, 31 m/sec, 79334760 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 95/224 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 9803743 m, 24 m/sec, 82821228 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 100/224 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-12 9803772 m, 5 m/sec, 86634509 t fired, .
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[[35mlola[0m][.] 43 CTL EXCL 4/233 7/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-14 1585859 m, 317171 m/sec, 3903897 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 5/249 3/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 670422 m, 134084 m/sec, 2914829 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 10/249 6/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 1374162 m, 140748 m/sec, 6017919 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 15/249 9/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 2007311 m, 126629 m/sec, 8820380 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 20/249 11/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 2671488 m, 132835 m/sec, 11766983 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 25/249 14/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 3335711 m, 132844 m/sec, 14717436 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 30/249 17/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 3990558 m, 130969 m/sec, 17628029 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 35/249 19/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 4629636 m, 127815 m/sec, 20474104 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 40/249 22/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 5258080 m, 125688 m/sec, 23273406 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 45/249 24/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 5880156 m, 124415 m/sec, 26045776 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 50/249 27/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 6505481 m, 125065 m/sec, 28833579 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 55/249 29/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 7125462 m, 123996 m/sec, 31597802 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 60/249 32/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 7739273 m, 122762 m/sec, 34332275 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 65/249 34/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 8348537 m, 121852 m/sec, 37044729 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 75/249 39/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 9551194 m, 119888 m/sec, 42387024 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 80/249 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 9793663 m, 48493 m/sec, 45458553 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 85/249 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 9798089 m, 885 m/sec, 48590261 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 90/249 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 9800627 m, 507 m/sec, 51763407 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 95/249 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 9802146 m, 303 m/sec, 54969944 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 100/249 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 9803256 m, 222 m/sec, 58310030 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 105/249 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-13 9803707 m, 90 m/sec, 61886338 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 1/282 1/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 96297 m, 19259 m/sec, 513717 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 6/282 5/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 1238426 m, 228425 m/sec, 7720076 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 11/282 10/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 2258331 m, 203981 m/sec, 14249521 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 16/282 13/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 3224118 m, 193157 m/sec, 20463990 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 21/282 17/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 4129635 m, 181103 m/sec, 26335475 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 26/282 21/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 5015228 m, 177118 m/sec, 32098677 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 31/282 24/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 5863839 m, 169722 m/sec, 37658594 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 36/282 27/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 6722100 m, 171652 m/sec, 43303434 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 41/282 31/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 7543536 m, 164287 m/sec, 48752693 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 46/282 34/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 8357290 m, 162750 m/sec, 54212218 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 51/282 37/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 9171760 m, 162894 m/sec, 59765081 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 56/282 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 9791137 m, 123875 m/sec, 65062350 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 61/282 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 9797019 m, 1176 m/sec, 68489378 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 66/282 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 9799889 m, 574 m/sec, 71825895 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 71/282 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 9801698 m, 361 m/sec, 75276193 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 76/282 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 9803046 m, 269 m/sec, 78818524 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 81/282 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-10 9803648 m, 120 m/sec, 82573144 t fired, .
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[[35mlola[0m][I] markings : 9803780
[[35mlola[0m][I] fired transitions : 86374112
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[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 355
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[[35mlola[0m][I] markings : 2115
[[35mlola[0m][I] fired transitions : 4151
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[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 10003
[[35mlola[0m][I] fired transitions : 34562
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[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-05
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[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-05
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[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 200
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[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00
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[[35mlola[0m][.] 1 CTL EXCL 1/550 1/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 227112 m, 45422 m/sec, 427995 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 6/550 9/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 2072346 m, 369046 m/sec, 5151938 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 11/550 14/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 3327050 m, 250940 m/sec, 9571323 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 16/550 18/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 4300439 m, 194677 m/sec, 13856204 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 21/550 21/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 5116456 m, 163203 m/sec, 18081083 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 26/550 24/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 5783356 m, 133380 m/sec, 22194827 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 31/550 26/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 6359371 m, 115203 m/sec, 26273767 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 36/550 28/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 6843562 m, 96838 m/sec, 30337525 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 41/550 30/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 7282428 m, 87773 m/sec, 34368997 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 46/550 31/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 7680119 m, 79538 m/sec, 38372445 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 51/550 33/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 8016732 m, 67322 m/sec, 42379657 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 56/550 34/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 8323114 m, 61276 m/sec, 46407412 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 61/550 35/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 8597975 m, 54972 m/sec, 50491008 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 66/550 36/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 8839650 m, 48335 m/sec, 54582059 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 71/550 37/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9052335 m, 42537 m/sec, 58639714 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 76/550 38/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9234224 m, 36377 m/sec, 62650073 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 81/550 38/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9381487 m, 29452 m/sec, 66666438 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 86/550 39/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9502401 m, 24182 m/sec, 70683806 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 91/550 39/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9601995 m, 19918 m/sec, 74740403 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 96/550 39/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9675158 m, 14632 m/sec, 78797847 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 101/550 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9734159 m, 11800 m/sec, 82939852 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 106/550 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9785473 m, 10262 m/sec, 87113229 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 111/550 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9802902 m, 3485 m/sec, 90699445 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 116/550 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9803142 m, 48 m/sec, 93765296 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 121/550 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9803328 m, 37 m/sec, 96859711 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 126/550 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9803476 m, 29 m/sec, 100029632 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 131/550 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9803603 m, 25 m/sec, 103149542 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 136/550 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9803707 m, 20 m/sec, 106442228 t fired, .
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[[35mlola[0m][.] TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15: CONJ 0 2 0 0 4 0 0 0
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[[35mlola[0m][.] 1 CTL EXCL 141/550 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00 9803763 m, 11 m/sec, 109918619 t fired, .
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[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 9803780
[[35mlola[0m][I] fired transitions : 110989879
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[[35mlola[0m][I] FINISHED task # 56 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 301
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[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 45 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15
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[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 251
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[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 45 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15
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[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-2023-15
[[35mlola[0m][I] result : false
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[[35mlola[0m][.] 4 CTL EXCL 3/1578 5/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 1055903 m, 211180 m/sec, 4717120 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 8/1578 10/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 2399324 m, 268684 m/sec, 11231971 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 13/1578 15/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 3587843 m, 237703 m/sec, 17316524 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 18/1578 19/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 4677075 m, 217846 m/sec, 23158191 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 23/1578 23/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 5713457 m, 207276 m/sec, 28846507 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 28/1578 27/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 6693822 m, 196073 m/sec, 34328608 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 33/1578 31/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 7618112 m, 184858 m/sec, 39537383 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 38/1578 35/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 8485838 m, 173545 m/sec, 44647270 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 43/1578 38/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 9270103 m, 156853 m/sec, 49710501 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 48/1578 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 9800738 m, 106127 m/sec, 54724345 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 53/1578 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 9802154 m, 283 m/sec, 58170243 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 58/1578 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 9802800 m, 129 m/sec, 61578316 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 63/1578 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 9803260 m, 92 m/sec, 65012417 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 68/1578 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 9803572 m, 62 m/sec, 68488281 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 73/1578 40/2000 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-01 9803749 m, 35 m/sec, 72195714 t fired, .
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 9803780
[[35mlola[0m][I] fired transitions : 76131058
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[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 3080 sec
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[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC00100vD-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 355
[[35mlola[0m][I] fired transitions : 460
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00100vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC00100vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575100338"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00100vD.tgz
mv TwoPhaseLocking-PT-nC00100vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;