About the Execution of LoLA for TwoPhaseLocking-PT-nC00050vN
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 352.384 | 16964.00 | 17634.00 | 115.10 | TTFTFFTFTFTTFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r423-smll-171690575100330.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TwoPhaseLocking-PT-nC00050vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690575100330
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 496K
-rw-r--r-- 1 mcc users 6.6K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 65K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 23 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 13 07:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 103K Apr 13 07:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 16K Apr 13 07:17 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 150K Apr 13 07:17 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 08:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.6K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-00
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-02
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-04
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-05
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-07
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-08
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-09
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-10
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-11
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-13
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-14
FORMULA_NAME TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717173483851
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01: CONJ true CONJ[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03: AGAF true state space /EFEG[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-05: EG false state space / EG[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-08: CONJ true CONJ[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12: EFAG false tscc_search[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 17 secs. Pages in use: 2
BK_STOP 1717173500815
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 15 (type EXCL) for 14 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 109 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 75 (type EQUN) for 56 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type EQUN) for 56 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 78 (type EQUN) for 26 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 75 (type EQUN) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 85 (type EQUN) for 17 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 77 (type EQUN) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 91 (type EQUN) for 23 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 78 (type EQUN) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 80 (type EQUN) for 26 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 91 (type EQUN) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 87 (type EQUN) for 17 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 85 (type EQUN) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 80 (type EQUN) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 87 (type EQUN) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 15 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 81676
[[35mlola[0m][I] fired transitions : 183149
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 66 (type EXCL) for 65 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 66 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 50
[[35mlola[0m][I] fired transitions : 49
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 62 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 81481
[[35mlola[0m][I] fired transitions : 182768
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 59 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 403741
[[35mlola[0m][I] fired transitions : 2871839
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 403741
[[35mlola[0m][I] fired transitions : 3272762
[[35mlola[0m][I] time used : 3
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 0/224 1/2000 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-09 4273 m, 854 m/sec, 22308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 403741
[[35mlola[0m][I] fired transitions : 3125287
[[35mlola[0m][I] time used : 3
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 36 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-08: CONJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 2/239 2/2000 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-08 403713 m, 80742 m/sec, 2551807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 403741
[[35mlola[0m][I] fired transitions : 2775321
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 522
[[35mlola[0m][I] fired transitions : 799
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 26 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 401290
[[35mlola[0m][I] fired transitions : 1975832
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 12 (type EXCL) for 3 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 12 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 403741
[[35mlola[0m][I] fired transitions : 2795171
[[35mlola[0m][I] time used : 3
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 3 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mTwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01: CONJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-08: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 1/358 1/2000 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01 234750 m, 46950 m/sec, 959861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 403741
[[35mlola[0m][I] fired transitions : 2517502
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 3 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 398 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 88 (type EXCL) for 23 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 447 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 88 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1051
[[35mlola[0m][I] fired transitions : 1674
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 82 (type EXCL) for 17 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 511 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 82 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8146
[[35mlola[0m][I] fired transitions : 17116
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 70 (type EXCL) for 56 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 597 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 11787
[[35mlola[0m][I] fired transitions : 28362
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 36 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 716 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 47501
[[35mlola[0m][I] fired transitions : 255124
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 1194 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 105
[[35mlola[0m][I] fired transitions : 105
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 21 (type EXCL) for 20 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 1791 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 21 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 18251
[[35mlola[0m][I] fired transitions : 55679
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 3583 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC00050vN-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 103
[[35mlola[0m][I] fired transitions : 333
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00050vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC00050vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690575100330"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00050vN.tgz
mv TwoPhaseLocking-PT-nC00050vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;