About the Execution of LoLA for TokenRing-PT-015
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.739 | 2354582.00 | 4922268.00 | 7677.60 | ?????TF???F????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r423-smll-171690574700170.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is TokenRing-PT-015, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-smll-171690574700170
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 39M
-rw-r--r-- 1 mcc users 219K Apr 11 19:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 1.1M Apr 11 19:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 1.7M Apr 11 19:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 6.2M Apr 11 19:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 117K Apr 23 08:02 LTLCardinality.txt
-rw-r--r-- 1 mcc users 412K Apr 23 08:02 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.2M Apr 23 08:02 LTLFireability.txt
-rw-r--r-- 1 mcc users 3.2M Apr 23 08:02 LTLFireability.xml
-rw-r--r-- 1 mcc users 595K Apr 11 20:28 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 3.0M Apr 11 20:28 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.2M Apr 11 19:59 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16M Apr 11 19:59 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 28K Apr 23 08:02 UpperBounds.txt
-rw-r--r-- 1 mcc users 71K Apr 23 08:02 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 1.7M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-00
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-01
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-02
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-03
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-04
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-05
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-06
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-07
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-08
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-09
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-10
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-11
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-12
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-13
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-14
FORMULA_NAME TokenRing-PT-015-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717106096531
FORMULA TokenRing-PT-015-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TokenRing-PT-015-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TokenRing-PT-015-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717108451113
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 31 (type CNST) for 30 TokenRing-PT-015-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 31 (type CNST) for TokenRing-PT-015-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTokenRing-PT-015-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-05: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-13: DISJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 TokenRing-PT-015-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 208 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mTokenRing-PT-015-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-03: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-05: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-13: DISJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 0/208 0/2000 TokenRing-PT-015-CTLFireability-2024-06 --
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for TokenRing-PT-015-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 293
[[35mlola[0m][I] fired transitions : 879
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 TokenRing-PT-015-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 221 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type FNDP) for 15 TokenRing-PT-015-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 15 TokenRing-PT-015-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for 39 TokenRing-PT-015-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type FNDP) for TokenRing-PT-015-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 57 (type EQUN) for TokenRing-PT-015-CTLFireability-2024-05 (obsolete)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTokenRing-PT-015-CTLFireability-2024-05: EF true findpath[0m
[[35mlola[0m][.] [1m[31mTokenRing-PT-015-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTokenRing-PT-015-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-13: DISJ 0 3 1 0 3 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 CTL EXCL 5/236 2/2000 TokenRing-PT-015-CTLFireability-2024-07 339091 m, 67818 m/sec, 1835437 t fired, .
[[35mlola[0m][.] 61 EF STEQ 1/3545 0/5 TokenRing-PT-015-CTLFireability-2024-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][I] FINISHED task # 61 (type EQUN) for TokenRing-PT-015-CTLFireability-2024-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mTokenRing-PT-015-CTLFireability-2024-05: EF true findpath[0m
[[35mlola[0m][.] [1m[31mTokenRing-PT-015-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTokenRing-PT-015-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-13: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 CTL EXCL 10/236 3/2000 TokenRing-PT-015-CTLFireability-2024-07 688721 m, 69926 m/sec, 3917561 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m[32mTokenRing-PT-015-CTLFireability-2024-05: EF true findpath[0m
[[35mlola[0m][.] [1m[31mTokenRing-PT-015-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTokenRing-PT-015-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-13: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 CTL EXCL 15/236 5/2000 TokenRing-PT-015-CTLFireability-2024-07 1023321 m, 66920 m/sec, 6065474 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for TokenRing-PT-015-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
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[[35mlola[0m][.] [1m[31mTokenRing-PT-015-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mTokenRing-PT-015-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-13: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 CTL EXCL 20/236 6/2000 TokenRing-PT-015-CTLFireability-2024-07 1367730 m, 68881 m/sec, 8239777 t fired, .
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[[35mlola[0m][.] [1m[31mTokenRing-PT-015-CTLFireability-2024-06: CTL false CTL model checker[0m
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[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-13: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 22 CTL EXCL 25/236 8/2000 TokenRing-PT-015-CTLFireability-2024-07 1714519 m, 69357 m/sec, 10394130 t fired, .
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[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-13: DISJ 0 3 0 0 4 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] TokenRing-PT-015-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 22 CTL EXCL 30/236 9/2000 TokenRing-PT-015-CTLFireability-2024-07 2031830 m, 63462 m/sec, 12616474 t fired, .
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[[35mlola[0m][.]
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[[35mlola[0m][.] 22 CTL EXCL 35/236 11/2000 TokenRing-PT-015-CTLFireability-2024-07 2347955 m, 63225 m/sec, 14810347 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 25/236 5/2000 TokenRing-PT-015-CTLFireability-2024-15 1116836 m, 44801 m/sec, 8833356 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 30/236 6/2000 TokenRing-PT-015-CTLFireability-2024-15 1338203 m, 44273 m/sec, 10708549 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 35/236 7/2000 TokenRing-PT-015-CTLFireability-2024-15 1563883 m, 45136 m/sec, 12556456 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 40/236 8/2000 TokenRing-PT-015-CTLFireability-2024-15 1781458 m, 43515 m/sec, 14428716 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 45/236 9/2000 TokenRing-PT-015-CTLFireability-2024-15 1995060 m, 42720 m/sec, 16357426 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 50/236 10/2000 TokenRing-PT-015-CTLFireability-2024-15 2199676 m, 40923 m/sec, 18303880 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 70/236 14/2000 TokenRing-PT-015-CTLFireability-2024-15 3052827 m, 40237 m/sec, 25681671 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 75/236 15/2000 TokenRing-PT-015-CTLFireability-2024-15 3269304 m, 43295 m/sec, 27548277 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 80/236 15/2000 TokenRing-PT-015-CTLFireability-2024-15 3479881 m, 42115 m/sec, 29446380 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 85/236 16/2000 TokenRing-PT-015-CTLFireability-2024-15 3684393 m, 40902 m/sec, 31387068 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 90/236 17/2000 TokenRing-PT-015-CTLFireability-2024-15 3886709 m, 40463 m/sec, 33302564 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 155/236 29/2000 TokenRing-PT-015-CTLFireability-2024-15 6648778 m, 40359 m/sec, 57876947 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 160/236 30/2000 TokenRing-PT-015-CTLFireability-2024-15 6839688 m, 38182 m/sec, 59831233 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 165/236 31/2000 TokenRing-PT-015-CTLFireability-2024-15 7053997 m, 42861 m/sec, 61702387 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 170/236 32/2000 TokenRing-PT-015-CTLFireability-2024-15 7260491 m, 41298 m/sec, 63551056 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 175/236 33/2000 TokenRing-PT-015-CTLFireability-2024-15 7469641 m, 41830 m/sec, 65434538 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 200/236 37/2000 TokenRing-PT-015-CTLFireability-2024-15 8461869 m, 39749 m/sec, 74993443 t fired, .
[[35mlola[0m][.] 59 EXEF EXCL 200/219 4/5 TokenRing-PT-015-CTLFireability-2024-13 1038769 m, 5077 m/sec, 5934813 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 205/236 38/2000 TokenRing-PT-015-CTLFireability-2024-15 8653321 m, 38290 m/sec, 76942718 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 210/236 38/2000 TokenRing-PT-015-CTLFireability-2024-15 8843817 m, 38099 m/sec, 78886038 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 215/236 39/2000 TokenRing-PT-015-CTLFireability-2024-15 9045221 m, 40280 m/sec, 80765212 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 220/236 40/2000 TokenRing-PT-015-CTLFireability-2024-15 9272531 m, 45462 m/sec, 82586920 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 225/236 41/2000 TokenRing-PT-015-CTLFireability-2024-15 9488936 m, 43281 m/sec, 84436518 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 4/2829 1/5 TokenRing-PT-015-CTLFireability-2024-15 220615 m, -1942950 m/sec, 1595115 t fired, .
[[35mlola[0m][.] 59 EXEF EXCL 25/219 1/5 TokenRing-PT-015-CTLFireability-2024-13 128634 m, 5225 m/sec, 622918 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 9/2829 2/5 TokenRing-PT-015-CTLFireability-2024-15 443307 m, 44538 m/sec, 3297540 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 14/2829 3/5 TokenRing-PT-015-CTLFireability-2024-15 661972 m, 43733 m/sec, 5086750 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 19/2829 4/5 TokenRing-PT-015-CTLFireability-2024-15 875074 m, 42620 m/sec, 6846986 t fired, .
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[[35mlola[0m][.] 54 CTL EXCL 24/2829 5/5 TokenRing-PT-015-CTLFireability-2024-15 1089202 m, 42825 m/sec, 8614781 t fired, .
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[[35mlola[0m][.] 59 EXEF EXCL 50/203 1/5 TokenRing-PT-015-CTLFireability-2024-13 259069 m, 5145 m/sec, 1344542 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 25/201 6/2000 TokenRing-PT-015-CTLFireability-2024-13 1248384 m, 50004 m/sec, 8674234 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 30/201 7/2000 TokenRing-PT-015-CTLFireability-2024-13 1489931 m, 48309 m/sec, 10434423 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 40/201 9/2000 TokenRing-PT-015-CTLFireability-2024-13 1959567 m, 46204 m/sec, 14061123 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 165/201 34/2000 TokenRing-PT-015-CTLFireability-2024-13 7839794 m, 44439 m/sec, 61143877 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 170/201 35/2000 TokenRing-PT-015-CTLFireability-2024-13 8058329 m, 43707 m/sec, 63049929 t fired, .
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[[35mlola[0m][.] 48 CTL EXCL 175/201 36/2000 TokenRing-PT-015-CTLFireability-2024-13 8276920 m, 43718 m/sec, 64931362 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TokenRing-PT-015"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is TokenRing-PT-015, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-smll-171690574700170"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TokenRing-PT-015.tgz
mv TokenRing-PT-015 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;