Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r404-tall-171690539700154.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-5568
Executing tool tapaal
Input is StigmergyCommit-PT-06a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r404-tall-171690539700154
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.2M
-rw-r--r-- 1 mcc users 5.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 57K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:59 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:59 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 07:59 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 23 07:59 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.9K Apr 11 17:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 106K Apr 11 17:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Apr 11 17:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Apr 11 17:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:59 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:59 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 1.8M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-00
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-01
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-02
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-03
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-04
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-05
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-06
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-07
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-08
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-09
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-10
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2024-11
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2023-12
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2023-13
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2023-14
FORMULA_NAME StigmergyCommit-PT-06a-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717007568221

tapaal
Got BK_BIN_PATH=/home/mcc/BenchKit/bin/
---> tapaal --- TAPAAL - v2.2024
Setting MODEL_PATH=.
Setting VERIFYPN=/home/mcc/BenchKit/bin/verifypn
Got BK_TIME_CONFINEMENT=3600
Setting TEMPDIR=/home/mcc/BenchKit/bin/tmp
Got BK_MEMORY_CONFINEMENT=16384
Limiting to 16265216 kB
Total timeout: 3590
Time left: 3590

*************************************
* TAPAAL verifying CTLFireability *
*************************************
TEMPDIR=/home/mcc/BenchKit/bin/tmp
QF=/home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3
MF=/home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO
Time left: 3590
---------------------------------------------------
Step -1: Stripping Colors
---------------------------------------------------
Verifying stripped models (16 in total)

Time left: 3590
---------------------------------------------------
Step 0: Parallel Simplification
---------------------------------------------------
Doing parallel simplification (16 in total)
Total simplification timout is 718 -- reduction timeout is 299
timeout 3590 /home/mcc/BenchKit/bin/verifypn -n -q 718 -l 29 -d 299 -z 4 -s OverApprox --binary-query-io 2 --write-simplified /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --write-reduced /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING STRUCTURAL_REDUCTION QUERY_REDUCTION SAT_SMT LP_APPROX
Query index 6 was solved

Query is NOT satisfied.
Solution found by parallel simplification (step 0)
Time left: 3589

---------------------------------------------------
Step 1: Parallel processing
---------------------------------------------------
Doing parallel verification of individual queries (15 in total)
Each query is verified by 4 parallel strategies for 299 seconds
------------------- QUERY 1 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved

Query is satisfied.

Spent 0.000238 on verification
@@@0.04,7708@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s BestFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 1 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING STRUCTURAL_REDUCTION QUERY_REDUCTION SAT_SMT EXPLICIT STATE_COMPRESSION STUBBORN_SETS
Time left: 3589
------------------- QUERY 2 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved

Query is NOT satisfied.

Spent 0.000271 on verification
@@@0.05,7744@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s BestFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 2 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING STRUCTURAL_REDUCTION QUERY_REDUCTION SAT_SMT EXPLICIT STATE_COMPRESSION STUBBORN_SETS
Time left: 3588
------------------- QUERY 3 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.036574 on verification
@@@0.06,58908@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s RPFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 3 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3588
------------------- QUERY 4 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.077356 on verification
@@@0.11,61028@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s BFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 4 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3588
------------------- QUERY 5 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.035051 on verification
@@@0.10,58648@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s RPFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 5 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3588
------------------- QUERY 6 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 22.8479 on verification
@@@22.95,949608@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s RPFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 6 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3564
------------------- QUERY 7 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.0558 on verification
@@@0.12,58860@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s DFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 7 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3564
------------------- QUERY 8 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 9.34168 on verification
@@@9.42,257068@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s DFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 8 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3554
------------------- QUERY 9 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 2.00532 on verification
@@@2.08,142124@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s DFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 9 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3552
------------------- QUERY 10 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 7.27801 on verification
@@@7.35,199172@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s RPFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 10 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3544
------------------- QUERY 11 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.055456 on verification
@@@0.12,58712@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s RPFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 11 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3544
------------------- QUERY 12 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.049088 on verification
@@@0.12,58896@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s BFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 12 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3544
------------------- QUERY 13 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.03911 on verification
@@@0.10,58708@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s DFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 13 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3544
------------------- QUERY 14 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.040039 on verification
@@@0.12,58880@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s DFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 14 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3543
------------------- QUERY 15 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.050706 on verification
@@@0.12,58632@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n '-s RPFS -q 0 -l 0 -d 119' /home/mcc/BenchKit/bin/tmp/tmp.8DquaVSHAO /home/mcc/BenchKit/bin/tmp/tmp.UgxaEj3uy3 --binary-query-io 1 -x 15 -n

FORMULA StigmergyCommit-PT-06a-CTLFireability-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3543
All queries are solved
Time left: 3543
terminated-with-cleanup

BK_STOP 1717007615658

--------------------
content from stderr:

CPN OverApproximation is only usable on colored models

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyCommit-PT-06a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="tapaal"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool tapaal"
echo " Input is StigmergyCommit-PT-06a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r404-tall-171690539700154"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/StigmergyCommit-PT-06a.tgz
mv StigmergyCommit-PT-06a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;