About the Execution of LoLA for Szymanski-PT-b02
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
4841.512 | 494312.00 | 1698847.00 | 422.90 | FTTFTFFTTTTFTTFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r401-tall-171690535300858.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Szymanski-PT-b02, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r401-tall-171690535300858
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.0M
-rw-r--r-- 1 mcc users 6.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Apr 23 08:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 23 08:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 23 08:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 23 08:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.8K Apr 11 15:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 76K Apr 11 15:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.9K Apr 11 15:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 87K Apr 11 15:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 08:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 23 08:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 3.7M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-00
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-01
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-02
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-03
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-04
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-05
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-06
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-07
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-08
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-09
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-10
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-11
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2023-12
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2023-13
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2023-14
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717182937211
FORMULA Szymanski-PT-b02-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2023-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mSzymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mSzymanski-PT-b02-CTLFireability-2024-01: EF true state space[0m
[[35mlola[0m] [1m[32mSzymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mSzymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mSzymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mSzymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mSzymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mSzymanski-PT-b02-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mSzymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF[0m
[[35mlola[0m] [1m[31mSzymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mSzymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mSzymanski-PT-b02-CTLFireability-2023-13: EF true state space[0m
[[35mlola[0m] [1m[31mSzymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mSzymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 494 secs. Pages in use: 2
BK_STOP 1717183431523
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 256 transitions removed,260 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 8 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 13 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 Szymanski-PT-b02-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 270
[[35mlola[0m][I] fired transitions : 612
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 Szymanski-PT-b02-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 275 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 269
[[35mlola[0m][I] fired transitions : 341
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 Szymanski-PT-b02-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 298 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 49 (type FNDP) for 3 Szymanski-PT-b02-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 53 (type EQUN) for 3 Szymanski-PT-b02-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 52 (type EQUN) for 30 Szymanski-PT-b02-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 1 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 3 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 1/255 1/2000 Szymanski-PT-b02-CTLFireability-2024-03 18183 m, 3636 m/sec, 151302 t fired, .
[[35mlola[0m][.] 49 EF FNDP 0/1791 0/5 Szymanski-PT-b02-CTLFireability-2024-01 --
[[35mlola[0m][.] 52 EF STEQ 0/1791 0/5 Szymanski-PT-b02-CTLFireability-2024-10 sara not yet started (preprocessing).
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[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 45797
[[35mlola[0m][I] fired transitions : 390576
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 30 Szymanski-PT-b02-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 275 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker[0m
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 3 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 4/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 4994 m, 998 m/sec, 9192 t fired, .
[[35mlola[0m][.] 49 EF FNDP 5/1790 0/5 Szymanski-PT-b02-CTLFireability-2024-01 63 attempts, .
[[35mlola[0m][.] 52 EF STEQ 5/1790 0/5 Szymanski-PT-b02-CTLFireability-2024-10 sara not yet started (preprocessing).
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[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker[0m
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 3 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 48 EXEF EXCL 9/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 12604 m, 1522 m/sec, 24075 t fired, .
[[35mlola[0m][.] 49 EF FNDP 10/1786 0/5 Szymanski-PT-b02-CTLFireability-2024-01 121 attempts, .
[[35mlola[0m][.] 52 EF STEQ 10/1786 0/5 Szymanski-PT-b02-CTLFireability-2024-10 sara not yet started (preprocessing).
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[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 50 (type FNDP) for 39 Szymanski-PT-b02-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 14/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 19930 m, 1465 m/sec, 39687 t fired, .
[[35mlola[0m][.] 49 EF FNDP 15/1778 0/5 Szymanski-PT-b02-CTLFireability-2024-01 179 attempts, .
[[35mlola[0m][.] 50 EF FNDP 2/3569 0/5 Szymanski-PT-b02-CTLFireability-2023-13 10 attempts, .
[[35mlola[0m][.] 53 EF STEQ 15/3569 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
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[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 48 EXEF EXCL 19/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 27068 m, 1427 m/sec, 56717 t fired, .
[[35mlola[0m][.] 49 EF FNDP 20/1776 0/5 Szymanski-PT-b02-CTLFireability-2024-01 226 attempts, .
[[35mlola[0m][.] 50 EF FNDP 7/3567 0/5 Szymanski-PT-b02-CTLFireability-2023-13 78 attempts, .
[[35mlola[0m][.] 53 EF STEQ 20/3567 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
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[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 24/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 34220 m, 1430 m/sec, 77073 t fired, .
[[35mlola[0m][.] 49 EF FNDP 25/1771 0/5 Szymanski-PT-b02-CTLFireability-2024-01 264 attempts, .
[[35mlola[0m][.] 50 EF FNDP 12/3562 0/5 Szymanski-PT-b02-CTLFireability-2023-13 138 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 29/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 41230 m, 1402 m/sec, 98020 t fired, .
[[35mlola[0m][.] 49 EF FNDP 30/1766 0/5 Szymanski-PT-b02-CTLFireability-2024-01 298 attempts, .
[[35mlola[0m][.] 50 EF FNDP 17/3557 0/5 Szymanski-PT-b02-CTLFireability-2023-13 212 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 34/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 48603 m, 1474 m/sec, 119350 t fired, .
[[35mlola[0m][.] 49 EF FNDP 35/1761 0/5 Szymanski-PT-b02-CTLFireability-2024-01 344 attempts, .
[[35mlola[0m][.] 50 EF FNDP 22/3552 0/5 Szymanski-PT-b02-CTLFireability-2023-13 266 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 39/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 55826 m, 1444 m/sec, 141687 t fired, .
[[35mlola[0m][.] 49 EF FNDP 40/1756 0/5 Szymanski-PT-b02-CTLFireability-2024-01 388 attempts, .
[[35mlola[0m][.] 50 EF FNDP 27/3547 0/5 Szymanski-PT-b02-CTLFireability-2023-13 326 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 44/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 63050 m, 1444 m/sec, 165460 t fired, .
[[35mlola[0m][.] 49 EF FNDP 45/1751 0/5 Szymanski-PT-b02-CTLFireability-2024-01 422 attempts, .
[[35mlola[0m][.] 50 EF FNDP 32/3542 0/5 Szymanski-PT-b02-CTLFireability-2023-13 403 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 49/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 70147 m, 1419 m/sec, 188288 t fired, .
[[35mlola[0m][.] 49 EF FNDP 50/1746 0/5 Szymanski-PT-b02-CTLFireability-2024-01 473 attempts, .
[[35mlola[0m][.] 50 EF FNDP 37/3537 0/5 Szymanski-PT-b02-CTLFireability-2023-13 450 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 55/1741 0/5 Szymanski-PT-b02-CTLFireability-2024-01 521 attempts, .
[[35mlola[0m][.] 50 EF FNDP 42/3532 0/5 Szymanski-PT-b02-CTLFireability-2023-13 505 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 60/1736 0/5 Szymanski-PT-b02-CTLFireability-2024-01 572 attempts, .
[[35mlola[0m][.] 50 EF FNDP 47/3527 0/5 Szymanski-PT-b02-CTLFireability-2023-13 573 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 65/1731 0/5 Szymanski-PT-b02-CTLFireability-2024-01 619 attempts, .
[[35mlola[0m][.] 50 EF FNDP 52/3522 0/5 Szymanski-PT-b02-CTLFireability-2023-13 636 attempts, .
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[[35mlola[0m][.] 49 EF FNDP 70/1726 0/5 Szymanski-PT-b02-CTLFireability-2024-01 672 attempts, .
[[35mlola[0m][.] 50 EF FNDP 57/3517 0/5 Szymanski-PT-b02-CTLFireability-2023-13 696 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 74/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 106336 m, 1496 m/sec, 311818 t fired, .
[[35mlola[0m][.] 49 EF FNDP 75/1721 0/5 Szymanski-PT-b02-CTLFireability-2024-01 710 attempts, .
[[35mlola[0m][.] 50 EF FNDP 62/3512 0/5 Szymanski-PT-b02-CTLFireability-2023-13 754 attempts, .
[[35mlola[0m][.] 53 EF STEQ 75/3512 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 48 EXEF EXCL 79/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 113545 m, 1441 m/sec, 337049 t fired, .
[[35mlola[0m][.] 49 EF FNDP 80/1716 0/5 Szymanski-PT-b02-CTLFireability-2024-01 742 attempts, .
[[35mlola[0m][.] 50 EF FNDP 67/3507 0/5 Szymanski-PT-b02-CTLFireability-2023-13 807 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 84/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 120927 m, 1476 m/sec, 363539 t fired, .
[[35mlola[0m][.] 49 EF FNDP 85/1711 0/5 Szymanski-PT-b02-CTLFireability-2024-01 788 attempts, .
[[35mlola[0m][.] 50 EF FNDP 72/3502 0/5 Szymanski-PT-b02-CTLFireability-2023-13 863 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 89/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 128222 m, 1459 m/sec, 392236 t fired, .
[[35mlola[0m][.] 49 EF FNDP 90/1706 0/5 Szymanski-PT-b02-CTLFireability-2024-01 836 attempts, .
[[35mlola[0m][.] 50 EF FNDP 77/3497 0/5 Szymanski-PT-b02-CTLFireability-2023-13 912 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 94/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 135356 m, 1426 m/sec, 422898 t fired, .
[[35mlola[0m][.] 49 EF FNDP 95/1701 0/5 Szymanski-PT-b02-CTLFireability-2024-01 883 attempts, .
[[35mlola[0m][.] 50 EF FNDP 82/3492 0/5 Szymanski-PT-b02-CTLFireability-2023-13 965 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 99/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 142335 m, 1395 m/sec, 455391 t fired, .
[[35mlola[0m][.] 49 EF FNDP 100/1696 0/5 Szymanski-PT-b02-CTLFireability-2024-01 925 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 110/1686 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1021 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 114/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 164590 m, 1528 m/sec, 615886 t fired, .
[[35mlola[0m][.] 49 EF FNDP 115/1681 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1070 attempts, .
[[35mlola[0m][.] 50 EF FNDP 102/3472 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1209 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 119/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 172188 m, 1519 m/sec, 641979 t fired, .
[[35mlola[0m][.] 49 EF FNDP 120/1676 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1111 attempts, .
[[35mlola[0m][.] 50 EF FNDP 107/3467 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1261 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 124/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 179123 m, 1387 m/sec, 665433 t fired, .
[[35mlola[0m][.] 49 EF FNDP 125/1671 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1151 attempts, .
[[35mlola[0m][.] 50 EF FNDP 112/3462 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1320 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 129/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 185722 m, 1319 m/sec, 689626 t fired, .
[[35mlola[0m][.] 49 EF FNDP 130/1666 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1207 attempts, .
[[35mlola[0m][.] 50 EF FNDP 117/3457 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1374 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 134/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 192120 m, 1279 m/sec, 713397 t fired, .
[[35mlola[0m][.] 49 EF FNDP 135/1661 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1243 attempts, .
[[35mlola[0m][.] 50 EF FNDP 122/3452 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1433 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 139/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 196795 m, 935 m/sec, 729850 t fired, .
[[35mlola[0m][.] 49 EF FNDP 140/1656 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1280 attempts, .
[[35mlola[0m][.] 50 EF FNDP 127/3447 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1457 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 144/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 199925 m, 626 m/sec, 741454 t fired, .
[[35mlola[0m][.] 49 EF FNDP 145/1651 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1330 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 149/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 203167 m, 648 m/sec, 753324 t fired, .
[[35mlola[0m][.] 49 EF FNDP 150/1646 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1372 attempts, .
[[35mlola[0m][.] 50 EF FNDP 137/3437 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1504 attempts, .
[[35mlola[0m][.] 53 EF STEQ 150/3437 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 154/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 206426 m, 651 m/sec, 765529 t fired, .
[[35mlola[0m][.] 49 EF FNDP 155/1641 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1426 attempts, .
[[35mlola[0m][.] 50 EF FNDP 142/3432 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1527 attempts, .
[[35mlola[0m][.] 53 EF STEQ 155/3432 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EXEF EXCL 159/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 209647 m, 644 m/sec, 778107 t fired, .
[[35mlola[0m][.] 49 EF FNDP 160/1636 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1476 attempts, .
[[35mlola[0m][.] 50 EF FNDP 147/3427 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1547 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 165/1631 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1531 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 170/1626 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1575 attempts, .
[[35mlola[0m][.] 50 EF FNDP 157/3417 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1633 attempts, .
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[[35mlola[0m][I] fired transitions : 840116
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[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 Szymanski-PT-b02-CTLFireability-2023-15
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 1/309 1/2000 Szymanski-PT-b02-CTLFireability-2023-14 50919 m, 10183 m/sec, 136662 t fired, .
[[35mlola[0m][.] 49 EF FNDP 175/1617 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1628 attempts, .
[[35mlola[0m][.] 50 EF FNDP 162/3408 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1684 attempts, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 6/309 2/2000 Szymanski-PT-b02-CTLFireability-2023-14 257164 m, 41249 m/sec, 1033722 t fired, .
[[35mlola[0m][.] 49 EF FNDP 180/1616 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1672 attempts, .
[[35mlola[0m][.] 50 EF FNDP 167/3407 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1736 attempts, .
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[[35mlola[0m][I] fired transitions : 1106816
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[[35mlola[0m][I] time limit : 340 sec
[[35mlola[0m][I] memory limit: 2000 pages
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[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
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[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF[0m
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 5/340 1/2000 Szymanski-PT-b02-CTLFireability-2023-12 145949 m, 29189 m/sec, 502553 t fired, .
[[35mlola[0m][.] 49 EF FNDP 185/1611 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1709 attempts, .
[[35mlola[0m][.] 50 EF FNDP 172/3402 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1787 attempts, .
[[35mlola[0m][.] 53 EF STEQ 185/3402 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for Szymanski-PT-b02-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 275702
[[35mlola[0m][I] fired transitions : 1101090
[[35mlola[0m][I] time used : 9
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 Szymanski-PT-b02-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 377 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 1/377 1/2000 Szymanski-PT-b02-CTLFireability-2024-11 35577 m, 7115 m/sec, 88226 t fired, .
[[35mlola[0m][.] 49 EF FNDP 190/1602 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1757 attempts, .
[[35mlola[0m][.] 50 EF FNDP 177/3393 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1833 attempts, .
[[35mlola[0m][.] 53 EF STEQ 190/3393 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 277943
[[35mlola[0m][I] fired transitions : 1108099
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 Szymanski-PT-b02-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 423 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 1/423 1/2000 Szymanski-PT-b02-CTLFireability-2024-08 21717 m, 4343 m/sec, 52721 t fired, .
[[35mlola[0m][.] 49 EF FNDP 195/1597 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1800 attempts, .
[[35mlola[0m][.] 50 EF FNDP 182/3388 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1887 attempts, .
[[35mlola[0m][.] 53 EF STEQ 195/3388 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
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[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 209198
[[35mlola[0m][I] fired transitions : 853601
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 Szymanski-PT-b02-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 483 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 CTL EXCL 1/483 1/2000 Szymanski-PT-b02-CTLFireability-2024-07 22139 m, 4427 m/sec, 53694 t fired, .
[[35mlola[0m][.] 49 EF FNDP 200/1592 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1845 attempts, .
[[35mlola[0m][.] 50 EF FNDP 187/3383 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1937 attempts, .
[[35mlola[0m][.] 53 EF STEQ 200/3383 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
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[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 186000
[[35mlola[0m][I] fired transitions : 769183
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 Szymanski-PT-b02-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 563 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 270
[[35mlola[0m][I] fired transitions : 342
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 Szymanski-PT-b02-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 675 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 1/675 1/2000 Szymanski-PT-b02-CTLFireability-2024-02 50939 m, 10187 m/sec, 136108 t fired, .
[[35mlola[0m][.] 49 EF FNDP 205/1587 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1897 attempts, .
[[35mlola[0m][.] 50 EF FNDP 192/3378 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1988 attempts, .
[[35mlola[0m][.] 53 EF STEQ 205/3378 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
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[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 238127
[[35mlola[0m][I] fired transitions : 962950
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 Szymanski-PT-b02-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 843 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 1/843 1/2000 Szymanski-PT-b02-CTLFireability-2024-00 10425 m, 2085 m/sec, 46622 t fired, .
[[35mlola[0m][.] 49 EF FNDP 210/1582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1940 attempts, .
[[35mlola[0m][.] 50 EF FNDP 197/3373 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2039 attempts, .
[[35mlola[0m][.] 53 EF STEQ 210/3373 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 6/843 1/2000 Szymanski-PT-b02-CTLFireability-2024-00 141033 m, 26121 m/sec, 758134 t fired, .
[[35mlola[0m][.] 49 EF FNDP 215/1581 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1981 attempts, .
[[35mlola[0m][.] 50 EF FNDP 202/3372 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2089 attempts, .
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[[35mlola[0m][I] fired transitions : 1231013
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[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker[0m
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[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker[0m
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 50 EF FNDP 207/3364 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2141 attempts, .
[[35mlola[0m][.] 53 EF STEQ 220/3364 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.] 56 EF EXCL 2/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 3361 m, 672 m/sec, 6359 t fired, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 53 EF STEQ 225/3362 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.] 56 EF EXCL 7/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 11106 m, 1549 m/sec, 21159 t fired, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 56 EF EXCL 12/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 18761 m, 1531 m/sec, 35273 t fired, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 56 EF EXCL 17/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 26401 m, 1528 m/sec, 53090 t fired, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 56 EF EXCL 22/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 34015 m, 1522 m/sec, 73001 t fired, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 56 EF EXCL 27/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 41541 m, 1505 m/sec, 95975 t fired, .
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[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 56 EF EXCL 107/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 160281 m, 1579 m/sec, 604203 t fired, .
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[[35mlola[0m][.] 56 EF EXCL 112/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 168002 m, 1544 m/sec, 631310 t fired, .
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[[35mlola[0m][.] 56 EF EXCL 117/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 175220 m, 1443 m/sec, 655356 t fired, .
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[[35mlola[0m][.] 56 EF EXCL 122/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 182072 m, 1370 m/sec, 680529 t fired, .
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[[35mlola[0m][.] 54 EF EXCL 4/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 5951 m, 1190 m/sec, 11114 t fired, .
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[[35mlola[0m][.] 54 EF EXCL 9/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 13356 m, 1481 m/sec, 26725 t fired, .
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[[35mlola[0m][.] 54 EF EXCL 14/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 20626 m, 1454 m/sec, 44070 t fired, .
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[[35mlola[0m][.] 54 EF EXCL 19/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 27911 m, 1457 m/sec, 63129 t fired, .
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[[35mlola[0m][.] 54 EF EXCL 24/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 35144 m, 1446 m/sec, 83412 t fired, .
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[[35mlola[0m][.] 54 EF EXCL 29/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 42338 m, 1438 m/sec, 104864 t fired, .
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[[35mlola[0m][.] 54 EF EXCL 39/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 56665 m, 1416 m/sec, 152351 t fired, .
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[[35mlola[0m][.] 54 EF EXCL 44/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 63812 m, 1429 m/sec, 176789 t fired, .
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[[35mlola[0m][.] 54 EF EXCL 54/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 78398 m, 1458 m/sec, 227975 t fired, .
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[[35mlola[0m][.] 54 EF EXCL 59/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 85693 m, 1459 m/sec, 256268 t fired, .
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[[35mlola[0m][.] 54 EF EXCL 104/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 151921 m, 1442 m/sec, 574115 t fired, .
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[[35mlola[0m][I] result : true
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[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-13: EF true state space[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 8/3115 1/2000 Szymanski-PT-b02-CTLFireability-2024-09 180954 m, 21333 m/sec, 1288796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 493 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 205315
[[35mlola[0m][I] fired transitions : 1448783
[[35mlola[0m][I] time used : 9
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Szymanski-PT-b02"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Szymanski-PT-b02, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r401-tall-171690535300858"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Szymanski-PT-b02.tgz
mv Szymanski-PT-b02 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;