fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r401-tall-171690535300858
Last Updated
July 7, 2024

About the Execution of LoLA for Szymanski-PT-b02

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
4841.512 494312.00 1698847.00 422.90 FTTFTFFTTTTFTTFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r401-tall-171690535300858.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Szymanski-PT-b02, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r401-tall-171690535300858
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.0M
-rw-r--r-- 1 mcc users 6.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Apr 23 08:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 23 08:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 23 08:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 23 08:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.8K Apr 11 15:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 76K Apr 11 15:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.9K Apr 11 15:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 87K Apr 11 15:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 08:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 23 08:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 3.7M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-00
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-01
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-02
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-03
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-04
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-05
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-06
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-07
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-08
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-09
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-10
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2024-11
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2023-12
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2023-13
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2023-14
FORMULA_NAME Szymanski-PT-b02-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717182937211

FORMULA Szymanski-PT-b02-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2023-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-b02-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2024-01: EF true state space
[lola] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2024-09: CTL true CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola]
[lola] Time elapsed: 494 secs. Pages in use: 2

BK_STOP 1717183431523

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 256 transitions removed,260 places removed
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 0 0 0 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 0 0 0 0 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 8 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 0 0 0 0 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 13 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 13 (type EXCL) for 12 Szymanski-PT-b02-CTLFireability-2024-04
[lola][I] time limit : 224 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 13 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-04
[lola][I] result : true
[lola][I] markings : 270
[lola][I] fired transitions : 612
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 19 (type EXCL) for 18 Szymanski-PT-b02-CTLFireability-2024-06
[lola][I] time limit : 275 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 19 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-06
[lola][I] result : false
[lola][I] markings : 269
[lola][I] fired transitions : 341
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 10 (type EXCL) for 9 Szymanski-PT-b02-CTLFireability-2024-03
[lola][I] time limit : 298 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 49 (type FNDP) for 3 Szymanski-PT-b02-CTLFireability-2024-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 53 (type EQUN) for 3 Szymanski-PT-b02-CTLFireability-2024-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 52 (type EQUN) for 30 Szymanski-PT-b02-CTLFireability-2024-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 1 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 3 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 1 0 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 10 CTL EXCL 1/255 1/2000 Szymanski-PT-b02-CTLFireability-2024-03 18183 m, 3636 m/sec, 151302 t fired, .
[lola][.] 49 EF FNDP 0/1791 0/5 Szymanski-PT-b02-CTLFireability-2024-01 --
[lola][.] 52 EF STEQ 0/1791 0/5 Szymanski-PT-b02-CTLFireability-2024-10 sara not yet started (preprocessing).
[lola][.] 53 EF STEQ 0/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 18 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 10 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-03
[lola][I] result : false
[lola][I] markings : 45797
[lola][I] fired transitions : 390576
[lola][I] time used : 2
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 48 (type EXCL) for 30 Szymanski-PT-b02-CTLFireability-2024-10
[lola][I] time limit : 275 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 3 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 4/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 4994 m, 998 m/sec, 9192 t fired, .
[lola][.] 49 EF FNDP 5/1790 0/5 Szymanski-PT-b02-CTLFireability-2024-01 63 attempts, .
[lola][.] 52 EF STEQ 5/1790 0/5 Szymanski-PT-b02-CTLFireability-2024-10 sara not yet started (preprocessing).
[lola][.] 53 EF STEQ 5/3581 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 23 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 3 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 9/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 12604 m, 1522 m/sec, 24075 t fired, .
[lola][.] 49 EF FNDP 10/1786 0/5 Szymanski-PT-b02-CTLFireability-2024-01 121 attempts, .
[lola][.] 52 EF STEQ 10/1786 0/5 Szymanski-PT-b02-CTLFireability-2024-10 sara not yet started (preprocessing).
[lola][.] 53 EF STEQ 10/3577 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 28 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 52 (type EQUN) for Szymanski-PT-b02-CTLFireability-2024-10
[lola][I] result : unknown
[lola][I] LAUNCH task # 50 (type FNDP) for 39 Szymanski-PT-b02-CTLFireability-2023-13
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 14/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 19930 m, 1465 m/sec, 39687 t fired, .
[lola][.] 49 EF FNDP 15/1778 0/5 Szymanski-PT-b02-CTLFireability-2024-01 179 attempts, .
[lola][.] 50 EF FNDP 2/3569 0/5 Szymanski-PT-b02-CTLFireability-2023-13 10 attempts, .
[lola][.] 53 EF STEQ 15/3569 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 33 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 19/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 27068 m, 1427 m/sec, 56717 t fired, .
[lola][.] 49 EF FNDP 20/1776 0/5 Szymanski-PT-b02-CTLFireability-2024-01 226 attempts, .
[lola][.] 50 EF FNDP 7/3567 0/5 Szymanski-PT-b02-CTLFireability-2023-13 78 attempts, .
[lola][.] 53 EF STEQ 20/3567 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 38 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 24/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 34220 m, 1430 m/sec, 77073 t fired, .
[lola][.] 49 EF FNDP 25/1771 0/5 Szymanski-PT-b02-CTLFireability-2024-01 264 attempts, .
[lola][.] 50 EF FNDP 12/3562 0/5 Szymanski-PT-b02-CTLFireability-2023-13 138 attempts, .
[lola][.] 53 EF STEQ 25/3562 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 43 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 29/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 41230 m, 1402 m/sec, 98020 t fired, .
[lola][.] 49 EF FNDP 30/1766 0/5 Szymanski-PT-b02-CTLFireability-2024-01 298 attempts, .
[lola][.] 50 EF FNDP 17/3557 0/5 Szymanski-PT-b02-CTLFireability-2023-13 212 attempts, .
[lola][.] 53 EF STEQ 30/3557 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 48 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 34/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 48603 m, 1474 m/sec, 119350 t fired, .
[lola][.] 49 EF FNDP 35/1761 0/5 Szymanski-PT-b02-CTLFireability-2024-01 344 attempts, .
[lola][.] 50 EF FNDP 22/3552 0/5 Szymanski-PT-b02-CTLFireability-2023-13 266 attempts, .
[lola][.] 53 EF STEQ 35/3552 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 53 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 39/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 55826 m, 1444 m/sec, 141687 t fired, .
[lola][.] 49 EF FNDP 40/1756 0/5 Szymanski-PT-b02-CTLFireability-2024-01 388 attempts, .
[lola][.] 50 EF FNDP 27/3547 0/5 Szymanski-PT-b02-CTLFireability-2023-13 326 attempts, .
[lola][.] 53 EF STEQ 40/3547 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 58 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 44/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 63050 m, 1444 m/sec, 165460 t fired, .
[lola][.] 49 EF FNDP 45/1751 0/5 Szymanski-PT-b02-CTLFireability-2024-01 422 attempts, .
[lola][.] 50 EF FNDP 32/3542 0/5 Szymanski-PT-b02-CTLFireability-2023-13 403 attempts, .
[lola][.] 53 EF STEQ 45/3542 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 63 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 49/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 70147 m, 1419 m/sec, 188288 t fired, .
[lola][.] 49 EF FNDP 50/1746 0/5 Szymanski-PT-b02-CTLFireability-2024-01 473 attempts, .
[lola][.] 50 EF FNDP 37/3537 0/5 Szymanski-PT-b02-CTLFireability-2023-13 450 attempts, .
[lola][.] 53 EF STEQ 50/3537 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 68 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 54/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 77327 m, 1436 m/sec, 213596 t fired, .
[lola][.] 49 EF FNDP 55/1741 0/5 Szymanski-PT-b02-CTLFireability-2024-01 521 attempts, .
[lola][.] 50 EF FNDP 42/3532 0/5 Szymanski-PT-b02-CTLFireability-2023-13 505 attempts, .
[lola][.] 53 EF STEQ 55/3532 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 73 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 59/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 84482 m, 1431 m/sec, 239308 t fired, .
[lola][.] 49 EF FNDP 60/1736 0/5 Szymanski-PT-b02-CTLFireability-2024-01 572 attempts, .
[lola][.] 50 EF FNDP 47/3527 0/5 Szymanski-PT-b02-CTLFireability-2023-13 573 attempts, .
[lola][.] 53 EF STEQ 60/3527 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 78 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 64/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 91453 m, 1394 m/sec, 263350 t fired, .
[lola][.] 49 EF FNDP 65/1731 0/5 Szymanski-PT-b02-CTLFireability-2024-01 619 attempts, .
[lola][.] 50 EF FNDP 52/3522 0/5 Szymanski-PT-b02-CTLFireability-2023-13 636 attempts, .
[lola][.] 53 EF STEQ 65/3522 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 83 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 69/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 98854 m, 1480 m/sec, 287342 t fired, .
[lola][.] 49 EF FNDP 70/1726 0/5 Szymanski-PT-b02-CTLFireability-2024-01 672 attempts, .
[lola][.] 50 EF FNDP 57/3517 0/5 Szymanski-PT-b02-CTLFireability-2023-13 696 attempts, .
[lola][.] 53 EF STEQ 70/3517 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 88 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 74/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 106336 m, 1496 m/sec, 311818 t fired, .
[lola][.] 49 EF FNDP 75/1721 0/5 Szymanski-PT-b02-CTLFireability-2024-01 710 attempts, .
[lola][.] 50 EF FNDP 62/3512 0/5 Szymanski-PT-b02-CTLFireability-2023-13 754 attempts, .
[lola][.] 53 EF STEQ 75/3512 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 93 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 79/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 113545 m, 1441 m/sec, 337049 t fired, .
[lola][.] 49 EF FNDP 80/1716 0/5 Szymanski-PT-b02-CTLFireability-2024-01 742 attempts, .
[lola][.] 50 EF FNDP 67/3507 0/5 Szymanski-PT-b02-CTLFireability-2023-13 807 attempts, .
[lola][.] 53 EF STEQ 80/3507 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 98 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 84/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 120927 m, 1476 m/sec, 363539 t fired, .
[lola][.] 49 EF FNDP 85/1711 0/5 Szymanski-PT-b02-CTLFireability-2024-01 788 attempts, .
[lola][.] 50 EF FNDP 72/3502 0/5 Szymanski-PT-b02-CTLFireability-2023-13 863 attempts, .
[lola][.] 53 EF STEQ 85/3502 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 103 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 89/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 128222 m, 1459 m/sec, 392236 t fired, .
[lola][.] 49 EF FNDP 90/1706 0/5 Szymanski-PT-b02-CTLFireability-2024-01 836 attempts, .
[lola][.] 50 EF FNDP 77/3497 0/5 Szymanski-PT-b02-CTLFireability-2023-13 912 attempts, .
[lola][.] 53 EF STEQ 90/3497 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 108 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 94/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 135356 m, 1426 m/sec, 422898 t fired, .
[lola][.] 49 EF FNDP 95/1701 0/5 Szymanski-PT-b02-CTLFireability-2024-01 883 attempts, .
[lola][.] 50 EF FNDP 82/3492 0/5 Szymanski-PT-b02-CTLFireability-2023-13 965 attempts, .
[lola][.] 53 EF STEQ 95/3492 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 113 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 99/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 142335 m, 1395 m/sec, 455391 t fired, .
[lola][.] 49 EF FNDP 100/1696 0/5 Szymanski-PT-b02-CTLFireability-2024-01 925 attempts, .
[lola][.] 50 EF FNDP 87/3487 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1033 attempts, .
[lola][.] 53 EF STEQ 100/3487 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 118 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 104/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 149642 m, 1461 m/sec, 520150 t fired, .
[lola][.] 49 EF FNDP 105/1691 0/5 Szymanski-PT-b02-CTLFireability-2024-01 971 attempts, .
[lola][.] 50 EF FNDP 92/3482 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1093 attempts, .
[lola][.] 53 EF STEQ 105/3482 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 123 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 109/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 156950 m, 1461 m/sec, 585951 t fired, .
[lola][.] 49 EF FNDP 110/1686 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1021 attempts, .
[lola][.] 50 EF FNDP 97/3477 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1150 attempts, .
[lola][.] 53 EF STEQ 110/3477 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 128 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 114/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 164590 m, 1528 m/sec, 615886 t fired, .
[lola][.] 49 EF FNDP 115/1681 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1070 attempts, .
[lola][.] 50 EF FNDP 102/3472 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1209 attempts, .
[lola][.] 53 EF STEQ 115/3472 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 133 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 119/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 172188 m, 1519 m/sec, 641979 t fired, .
[lola][.] 49 EF FNDP 120/1676 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1111 attempts, .
[lola][.] 50 EF FNDP 107/3467 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1261 attempts, .
[lola][.] 53 EF STEQ 120/3467 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 138 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 124/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 179123 m, 1387 m/sec, 665433 t fired, .
[lola][.] 49 EF FNDP 125/1671 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1151 attempts, .
[lola][.] 50 EF FNDP 112/3462 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1320 attempts, .
[lola][.] 53 EF STEQ 125/3462 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 143 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 129/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 185722 m, 1319 m/sec, 689626 t fired, .
[lola][.] 49 EF FNDP 130/1666 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1207 attempts, .
[lola][.] 50 EF FNDP 117/3457 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1374 attempts, .
[lola][.] 53 EF STEQ 130/3457 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 148 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 134/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 192120 m, 1279 m/sec, 713397 t fired, .
[lola][.] 49 EF FNDP 135/1661 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1243 attempts, .
[lola][.] 50 EF FNDP 122/3452 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1433 attempts, .
[lola][.] 53 EF STEQ 135/3452 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 153 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 139/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 196795 m, 935 m/sec, 729850 t fired, .
[lola][.] 49 EF FNDP 140/1656 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1280 attempts, .
[lola][.] 50 EF FNDP 127/3447 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1457 attempts, .
[lola][.] 53 EF STEQ 140/3447 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 158 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 144/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 199925 m, 626 m/sec, 741454 t fired, .
[lola][.] 49 EF FNDP 145/1651 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1330 attempts, .
[lola][.] 50 EF FNDP 132/3442 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1475 attempts, .
[lola][.] 53 EF STEQ 145/3442 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 163 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 149/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 203167 m, 648 m/sec, 753324 t fired, .
[lola][.] 49 EF FNDP 150/1646 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1372 attempts, .
[lola][.] 50 EF FNDP 137/3437 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1504 attempts, .
[lola][.] 53 EF STEQ 150/3437 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 168 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 154/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 206426 m, 651 m/sec, 765529 t fired, .
[lola][.] 49 EF FNDP 155/1641 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1426 attempts, .
[lola][.] 50 EF FNDP 142/3432 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1527 attempts, .
[lola][.] 53 EF STEQ 155/3432 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 173 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 159/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 209647 m, 644 m/sec, 778107 t fired, .
[lola][.] 49 EF FNDP 160/1636 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1476 attempts, .
[lola][.] 50 EF FNDP 147/3427 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1547 attempts, .
[lola][.] 53 EF STEQ 160/3427 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 178 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 164/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 215415 m, 1153 m/sec, 799278 t fired, .
[lola][.] 49 EF FNDP 165/1631 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1531 attempts, .
[lola][.] 50 EF FNDP 152/3422 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1592 attempts, .
[lola][.] 53 EF STEQ 165/3422 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 183 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF 0 0 1 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 EXEF EXCL 169/275 1/2000 Szymanski-PT-b02-CTLFireability-2024-10 221604 m, 1237 m/sec, 822313 t fired, .
[lola][.] 49 EF FNDP 170/1626 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1575 attempts, .
[lola][.] 50 EF FNDP 157/3417 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1633 attempts, .
[lola][.] 53 EF STEQ 170/3417 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 188 secs. Pages in use: 1
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 48 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-10
[lola][I] result : true
[lola][I] markings : 226592
[lola][I] fired transitions : 840116
[lola][I] time used : 173
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 46 (type EXCL) for 45 Szymanski-PT-b02-CTLFireability-2023-15
[lola][I] time limit : 284 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 46 (type EXCL) for Szymanski-PT-b02-CTLFireability-2023-15
[lola][I] result : true
[lola][I] markings : 33
[lola][I] fired transitions : 165
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 43 (type EXCL) for 42 Szymanski-PT-b02-CTLFireability-2023-14
[lola][I] time limit : 309 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 43 CTL EXCL 1/309 1/2000 Szymanski-PT-b02-CTLFireability-2023-14 50919 m, 10183 m/sec, 136662 t fired, .
[lola][.] 49 EF FNDP 175/1617 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1628 attempts, .
[lola][.] 50 EF FNDP 162/3408 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1684 attempts, .
[lola][.] 53 EF STEQ 175/3408 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 193 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 43 CTL EXCL 6/309 2/2000 Szymanski-PT-b02-CTLFireability-2023-14 257164 m, 41249 m/sec, 1033722 t fired, .
[lola][.] 49 EF FNDP 180/1616 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1672 attempts, .
[lola][.] 50 EF FNDP 167/3407 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1736 attempts, .
[lola][.] 53 EF STEQ 180/3407 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 198 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 43 (type EXCL) for Szymanski-PT-b02-CTLFireability-2023-14
[lola][I] result : false
[lola][I] markings : 277418
[lola][I] fired transitions : 1106816
[lola][I] time used : 6
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 37 (type EXCL) for 36 Szymanski-PT-b02-CTLFireability-2023-12
[lola][I] time limit : 340 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 37 CTL EXCL 5/340 1/2000 Szymanski-PT-b02-CTLFireability-2023-12 145949 m, 29189 m/sec, 502553 t fired, .
[lola][.] 49 EF FNDP 185/1611 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1709 attempts, .
[lola][.] 50 EF FNDP 172/3402 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1787 attempts, .
[lola][.] 53 EF STEQ 185/3402 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 203 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 37 (type EXCL) for Szymanski-PT-b02-CTLFireability-2023-12
[lola][I] result : true
[lola][I] markings : 275702
[lola][I] fired transitions : 1101090
[lola][I] time used : 9
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 34 (type EXCL) for 33 Szymanski-PT-b02-CTLFireability-2024-11
[lola][I] time limit : 377 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 34 CTL EXCL 1/377 1/2000 Szymanski-PT-b02-CTLFireability-2024-11 35577 m, 7115 m/sec, 88226 t fired, .
[lola][.] 49 EF FNDP 190/1602 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1757 attempts, .
[lola][.] 50 EF FNDP 177/3393 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1833 attempts, .
[lola][.] 53 EF STEQ 190/3393 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 208 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 34 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-11
[lola][I] result : false
[lola][I] markings : 277943
[lola][I] fired transitions : 1108099
[lola][I] time used : 5
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 25 (type EXCL) for 24 Szymanski-PT-b02-CTLFireability-2024-08
[lola][I] time limit : 423 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 1/423 1/2000 Szymanski-PT-b02-CTLFireability-2024-08 21717 m, 4343 m/sec, 52721 t fired, .
[lola][.] 49 EF FNDP 195/1597 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1800 attempts, .
[lola][.] 50 EF FNDP 182/3388 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1887 attempts, .
[lola][.] 53 EF STEQ 195/3388 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 213 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 25 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-08
[lola][I] result : true
[lola][I] markings : 209198
[lola][I] fired transitions : 853601
[lola][I] time used : 5
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 22 (type EXCL) for 21 Szymanski-PT-b02-CTLFireability-2024-07
[lola][I] time limit : 483 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 22 CTL EXCL 1/483 1/2000 Szymanski-PT-b02-CTLFireability-2024-07 22139 m, 4427 m/sec, 53694 t fired, .
[lola][.] 49 EF FNDP 200/1592 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1845 attempts, .
[lola][.] 50 EF FNDP 187/3383 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1937 attempts, .
[lola][.] 53 EF STEQ 200/3383 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 218 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 22 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-07
[lola][I] result : true
[lola][I] markings : 186000
[lola][I] fired transitions : 769183
[lola][I] time used : 5
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 16 (type EXCL) for 15 Szymanski-PT-b02-CTLFireability-2024-05
[lola][I] time limit : 563 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 16 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-05
[lola][I] result : false
[lola][I] markings : 270
[lola][I] fired transitions : 342
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 7 (type EXCL) for 6 Szymanski-PT-b02-CTLFireability-2024-02
[lola][I] time limit : 675 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 7 CTL EXCL 1/675 1/2000 Szymanski-PT-b02-CTLFireability-2024-02 50939 m, 10187 m/sec, 136108 t fired, .
[lola][.] 49 EF FNDP 205/1587 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1897 attempts, .
[lola][.] 50 EF FNDP 192/3378 0/5 Szymanski-PT-b02-CTLFireability-2023-13 1988 attempts, .
[lola][.] 53 EF STEQ 205/3378 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 223 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 7 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-02
[lola][I] result : true
[lola][I] markings : 238127
[lola][I] fired transitions : 962950
[lola][I] time used : 5
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 1 (type EXCL) for 0 Szymanski-PT-b02-CTLFireability-2024-00
[lola][I] time limit : 843 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 1 CTL EXCL 1/843 1/2000 Szymanski-PT-b02-CTLFireability-2024-00 10425 m, 2085 m/sec, 46622 t fired, .
[lola][.] 49 EF FNDP 210/1582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1940 attempts, .
[lola][.] 50 EF FNDP 197/3373 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2039 attempts, .
[lola][.] 53 EF STEQ 210/3373 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 228 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 1 CTL EXCL 6/843 1/2000 Szymanski-PT-b02-CTLFireability-2024-00 141033 m, 26121 m/sec, 758134 t fired, .
[lola][.] 49 EF FNDP 215/1581 0/5 Szymanski-PT-b02-CTLFireability-2024-01 1981 attempts, .
[lola][.] 50 EF FNDP 202/3372 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2089 attempts, .
[lola][.] 53 EF STEQ 215/3372 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 233 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 1 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-00
[lola][I] result : false
[lola][I] markings : 203043
[lola][I] fired transitions : 1231013
[lola][I] time used : 9
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 56 (type EXCL) for 39 Szymanski-PT-b02-CTLFireability-2023-13
[lola][I] time limit : 1121 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 220/1573 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2032 attempts, .
[lola][.] 50 EF FNDP 207/3364 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2141 attempts, .
[lola][.] 53 EF STEQ 220/3364 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 2/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 3361 m, 672 m/sec, 6359 t fired, .
[lola][.]
[lola][.] Time elapsed: 238 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 225/1571 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2082 attempts, .
[lola][.] 50 EF FNDP 212/3362 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2189 attempts, .
[lola][.] 53 EF STEQ 225/3362 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 7/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 11106 m, 1549 m/sec, 21159 t fired, .
[lola][.]
[lola][.] Time elapsed: 243 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 230/1566 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2139 attempts, .
[lola][.] 50 EF FNDP 217/3357 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2248 attempts, .
[lola][.] 53 EF STEQ 230/3357 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 12/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 18761 m, 1531 m/sec, 35273 t fired, .
[lola][.]
[lola][.] Time elapsed: 248 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 235/1561 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2189 attempts, .
[lola][.] 50 EF FNDP 222/3352 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2294 attempts, .
[lola][.] 53 EF STEQ 235/3352 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 17/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 26401 m, 1528 m/sec, 53090 t fired, .
[lola][.]
[lola][.] Time elapsed: 253 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 240/1556 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2229 attempts, .
[lola][.] 50 EF FNDP 227/3347 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2345 attempts, .
[lola][.] 53 EF STEQ 240/3347 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 22/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 34015 m, 1522 m/sec, 73001 t fired, .
[lola][.]
[lola][.] Time elapsed: 258 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 245/1551 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2283 attempts, .
[lola][.] 50 EF FNDP 232/3342 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2395 attempts, .
[lola][.] 53 EF STEQ 245/3342 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 27/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 41541 m, 1505 m/sec, 95975 t fired, .
[lola][.]
[lola][.] Time elapsed: 263 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 250/1546 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2324 attempts, .
[lola][.] 50 EF FNDP 237/3337 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2440 attempts, .
[lola][.] 53 EF STEQ 250/3337 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 32/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 49102 m, 1512 m/sec, 120143 t fired, .
[lola][.]
[lola][.] Time elapsed: 268 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 255/1541 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2380 attempts, .
[lola][.] 50 EF FNDP 242/3332 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2493 attempts, .
[lola][.] 53 EF STEQ 255/3332 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 37/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 56585 m, 1496 m/sec, 144304 t fired, .
[lola][.]
[lola][.] Time elapsed: 273 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 260/1536 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2408 attempts, .
[lola][.] 50 EF FNDP 247/3327 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2545 attempts, .
[lola][.] 53 EF STEQ 260/3327 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 42/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 63980 m, 1479 m/sec, 170247 t fired, .
[lola][.]
[lola][.] Time elapsed: 278 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 265/1531 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2447 attempts, .
[lola][.] 50 EF FNDP 252/3322 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2593 attempts, .
[lola][.] 53 EF STEQ 265/3322 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 47/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 71227 m, 1449 m/sec, 194919 t fired, .
[lola][.]
[lola][.] Time elapsed: 283 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 270/1526 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2484 attempts, .
[lola][.] 50 EF FNDP 257/3317 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2634 attempts, .
[lola][.] 53 EF STEQ 270/3317 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 52/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 78408 m, 1436 m/sec, 219797 t fired, .
[lola][.]
[lola][.] Time elapsed: 288 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 275/1521 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2518 attempts, .
[lola][.] 50 EF FNDP 262/3312 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2680 attempts, .
[lola][.] 53 EF STEQ 275/3312 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 57/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 85583 m, 1435 m/sec, 244775 t fired, .
[lola][.]
[lola][.] Time elapsed: 293 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 280/1516 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2563 attempts, .
[lola][.] 50 EF FNDP 267/3307 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2720 attempts, .
[lola][.] 53 EF STEQ 280/3307 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 62/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 92973 m, 1478 m/sec, 268668 t fired, .
[lola][.]
[lola][.] Time elapsed: 298 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 285/1511 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2600 attempts, .
[lola][.] 50 EF FNDP 272/3302 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2770 attempts, .
[lola][.] 53 EF STEQ 285/3302 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 67/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 100327 m, 1470 m/sec, 293721 t fired, .
[lola][.]
[lola][.] Time elapsed: 303 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 290/1506 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2645 attempts, .
[lola][.] 50 EF FNDP 277/3297 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2812 attempts, .
[lola][.] 53 EF STEQ 290/3297 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 72/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 107676 m, 1469 m/sec, 320024 t fired, .
[lola][.]
[lola][.] Time elapsed: 308 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 295/1501 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2680 attempts, .
[lola][.] 50 EF FNDP 282/3292 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2862 attempts, .
[lola][.] 53 EF STEQ 295/3292 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 77/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 115230 m, 1510 m/sec, 347187 t fired, .
[lola][.]
[lola][.] Time elapsed: 313 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 300/1496 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2726 attempts, .
[lola][.] 50 EF FNDP 287/3287 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2911 attempts, .
[lola][.] 53 EF STEQ 300/3287 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 82/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 122696 m, 1493 m/sec, 375600 t fired, .
[lola][.]
[lola][.] Time elapsed: 318 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 305/1491 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2762 attempts, .
[lola][.] 50 EF FNDP 292/3282 0/5 Szymanski-PT-b02-CTLFireability-2023-13 2958 attempts, .
[lola][.] 53 EF STEQ 305/3282 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 87/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 130167 m, 1494 m/sec, 405980 t fired, .
[lola][.]
[lola][.] Time elapsed: 323 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 310/1486 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2797 attempts, .
[lola][.] 50 EF FNDP 297/3277 0/5 Szymanski-PT-b02-CTLFireability-2023-13 3000 attempts, .
[lola][.] 53 EF STEQ 310/3277 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 92/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 137619 m, 1490 m/sec, 443283 t fired, .
[lola][.]
[lola][.] Time elapsed: 328 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 315/1481 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2836 attempts, .
[lola][.] 50 EF FNDP 302/3272 0/5 Szymanski-PT-b02-CTLFireability-2023-13 3065 attempts, .
[lola][.] 53 EF STEQ 315/3272 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 97/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 145104 m, 1497 m/sec, 489296 t fired, .
[lola][.]
[lola][.] Time elapsed: 333 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 320/1476 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2878 attempts, .
[lola][.] 50 EF FNDP 307/3267 0/5 Szymanski-PT-b02-CTLFireability-2023-13 3102 attempts, .
[lola][.] 53 EF STEQ 320/3267 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 102/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 152386 m, 1456 m/sec, 573326 t fired, .
[lola][.]
[lola][.] Time elapsed: 338 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 325/1471 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2923 attempts, .
[lola][.] 50 EF FNDP 312/3262 0/5 Szymanski-PT-b02-CTLFireability-2023-13 3154 attempts, .
[lola][.] 53 EF STEQ 325/3262 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 107/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 160281 m, 1579 m/sec, 604203 t fired, .
[lola][.]
[lola][.] Time elapsed: 343 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 330/1466 0/5 Szymanski-PT-b02-CTLFireability-2024-01 2975 attempts, .
[lola][.] 50 EF FNDP 317/3257 0/5 Szymanski-PT-b02-CTLFireability-2023-13 3204 attempts, .
[lola][.] 53 EF STEQ 330/3257 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 112/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 168002 m, 1544 m/sec, 631310 t fired, .
[lola][.]
[lola][.] Time elapsed: 348 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 335/1461 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3023 attempts, .
[lola][.] 50 EF FNDP 322/3252 0/5 Szymanski-PT-b02-CTLFireability-2023-13 3260 attempts, .
[lola][.] 53 EF STEQ 335/3252 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 117/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 175220 m, 1443 m/sec, 655356 t fired, .
[lola][.]
[lola][.] Time elapsed: 353 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 1 2 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF 0 1 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 340/1456 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3063 attempts, .
[lola][.] 50 EF FNDP 327/3247 0/5 Szymanski-PT-b02-CTLFireability-2023-13 3324 attempts, .
[lola][.] 53 EF STEQ 340/3247 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 56 EF EXCL 122/1121 1/2000 Szymanski-PT-b02-CTLFireability-2023-13 182072 m, 1370 m/sec, 680529 t fired, .
[lola][.]
[lola][.] Time elapsed: 358 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 56 (type EXCL) for Szymanski-PT-b02-CTLFireability-2023-13
[lola][I] result : true
[lola][I] markings : 183386
[lola][I] fired transitions : 685248
[lola][I] time used : 123
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 50 (type FNDP) for Szymanski-PT-b02-CTLFireability-2023-13 (obsolete)
[lola][I] LAUNCH task # 54 (type EXCL) for 3 Szymanski-PT-b02-CTLFireability-2024-01
[lola][I] time limit : 1620 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 50 (type FNDP) for Szymanski-PT-b02-CTLFireability-2023-13
[lola][I] result : unknown
[lola][I] tried executions : 3339
[lola][I] time used : 328
[lola][I] memory pages used : 0
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 3 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 345/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3118 attempts, .
[lola][.] 53 EF STEQ 345/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 54 EF EXCL 4/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 5951 m, 1190 m/sec, 11114 t fired, .
[lola][.]
[lola][.] Time elapsed: 363 secs. Pages in use: 2
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 3 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 350/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3159 attempts, .
[lola][.] 53 EF STEQ 350/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 54 EF EXCL 9/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 13356 m, 1481 m/sec, 26725 t fired, .
[lola][.]
[lola][.] Time elapsed: 368 secs. Pages in use: 2
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 3 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 355/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3210 attempts, .
[lola][.] 53 EF STEQ 355/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 54 EF EXCL 14/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 20626 m, 1454 m/sec, 44070 t fired, .
[lola][.]
[lola][.] Time elapsed: 373 secs. Pages in use: 2
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 3 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 360/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3258 attempts, .
[lola][.] 53 EF STEQ 360/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 54 EF EXCL 19/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 27911 m, 1457 m/sec, 63129 t fired, .
[lola][.]
[lola][.] Time elapsed: 378 secs. Pages in use: 2
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 3 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 365/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3305 attempts, .
[lola][.] 53 EF STEQ 365/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 54 EF EXCL 24/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 35144 m, 1446 m/sec, 83412 t fired, .
[lola][.]
[lola][.] Time elapsed: 383 secs. Pages in use: 2
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 3 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 370/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3354 attempts, .
[lola][.] 53 EF STEQ 370/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 54 EF EXCL 29/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 42338 m, 1438 m/sec, 104864 t fired, .
[lola][.]
[lola][.] Time elapsed: 388 secs. Pages in use: 2
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 3 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 375/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3402 attempts, .
[lola][.] 53 EF STEQ 375/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 54 EF EXCL 34/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 49581 m, 1448 m/sec, 129286 t fired, .
[lola][.]
[lola][.] Time elapsed: 393 secs. Pages in use: 2
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 3 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 380/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3436 attempts, .
[lola][.] 53 EF STEQ 380/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 54 EF EXCL 39/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 56665 m, 1416 m/sec, 152351 t fired, .
[lola][.]
[lola][.] Time elapsed: 398 secs. Pages in use: 2
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 3 0 1 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 385/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3480 attempts, .
[lola][.] 53 EF STEQ 385/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 sara not yet started (preprocessing).
[lola][.] 54 EF EXCL 44/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 63812 m, 1429 m/sec, 176789 t fired, .
[lola][.]
[lola][.] Time elapsed: 403 secs. Pages in use: 2
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] FINISHED task # 53 (type EQUN) for Szymanski-PT-b02-CTLFireability-2024-01
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 390/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3520 attempts, .
[lola][.] 54 EF EXCL 49/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 71106 m, 1458 m/sec, 201187 t fired, .
[lola][.]
[lola][.] Time elapsed: 408 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 395/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3566 attempts, .
[lola][.] 54 EF EXCL 54/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 78398 m, 1458 m/sec, 227975 t fired, .
[lola][.]
[lola][.] Time elapsed: 413 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 400/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3607 attempts, .
[lola][.] 54 EF EXCL 59/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 85693 m, 1459 m/sec, 256268 t fired, .
[lola][.]
[lola][.] Time elapsed: 418 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 405/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3648 attempts, .
[lola][.] 54 EF EXCL 64/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 92918 m, 1445 m/sec, 281145 t fired, .
[lola][.]
[lola][.] Time elapsed: 423 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 410/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3688 attempts, .
[lola][.] 54 EF EXCL 69/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 100297 m, 1475 m/sec, 306252 t fired, .
[lola][.]
[lola][.] Time elapsed: 428 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 415/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3725 attempts, .
[lola][.] 54 EF EXCL 74/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 107870 m, 1514 m/sec, 333514 t fired, .
[lola][.]
[lola][.] Time elapsed: 433 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 420/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3776 attempts, .
[lola][.] 54 EF EXCL 79/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 115300 m, 1486 m/sec, 361813 t fired, .
[lola][.]
[lola][.] Time elapsed: 438 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 425/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3820 attempts, .
[lola][.] 54 EF EXCL 84/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 122851 m, 1510 m/sec, 392397 t fired, .
[lola][.]
[lola][.] Time elapsed: 443 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 430/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3855 attempts, .
[lola][.] 54 EF EXCL 89/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 130140 m, 1457 m/sec, 422203 t fired, .
[lola][.]
[lola][.] Time elapsed: 448 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 435/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3902 attempts, .
[lola][.] 54 EF EXCL 94/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 137361 m, 1444 m/sec, 459328 t fired, .
[lola][.]
[lola][.] Time elapsed: 453 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 440/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3944 attempts, .
[lola][.] 54 EF EXCL 99/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 144707 m, 1469 m/sec, 501819 t fired, .
[lola][.]
[lola][.] Time elapsed: 458 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 445/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 3992 attempts, .
[lola][.] 54 EF EXCL 104/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 151921 m, 1442 m/sec, 574115 t fired, .
[lola][.]
[lola][.] Time elapsed: 463 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 450/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 4042 attempts, .
[lola][.] 54 EF EXCL 109/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 159608 m, 1537 m/sec, 604385 t fired, .
[lola][.]
[lola][.] Time elapsed: 468 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 455/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 4092 attempts, .
[lola][.] 54 EF EXCL 114/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 167253 m, 1529 m/sec, 631569 t fired, .
[lola][.]
[lola][.] Time elapsed: 473 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 460/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 4129 attempts, .
[lola][.] 54 EF EXCL 119/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 174592 m, 1467 m/sec, 655293 t fired, .
[lola][.]
[lola][.] Time elapsed: 478 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF 0 0 2 0 2 0 0 0
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EF FNDP 465/3582 0/5 Szymanski-PT-b02-CTLFireability-2024-01 4175 attempts, .
[lola][.] 54 EF EXCL 124/1620 1/2000 Szymanski-PT-b02-CTLFireability-2024-01 181370 m, 1355 m/sec, 680252 t fired, .
[lola][.]
[lola][.] Time elapsed: 483 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I] FINISHED task # 54 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-01
[lola][I] result : true
[lola][I] markings : 183880
[lola][I] fired transitions : 689239
[lola][I] time used : 126
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 49 (type FNDP) for Szymanski-PT-b02-CTLFireability-2024-01 (obsolete)
[lola][I] LAUNCH task # 28 (type EXCL) for 27 Szymanski-PT-b02-CTLFireability-2024-09
[lola][I] time limit : 3115 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 49 (type FNDP) for Szymanski-PT-b02-CTLFireability-2024-01
[lola][I] result : unknown
[lola][I] tried executions : 4187
[lola][I] time used : 467
[lola][I] memory pages used : 0
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 3/3115 1/2000 Szymanski-PT-b02-CTLFireability-2024-09 74286 m, 14857 m/sec, 443668 t fired, .
[lola][.]
[lola][.] Time elapsed: 488 secs. Pages in use: 2
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-b02-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-01: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-06: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2024-10: EXEF true state space /EXEF
[lola][.] Szymanski-PT-b02-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-13: EF true state space
[lola][.] Szymanski-PT-b02-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] Szymanski-PT-b02-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-b02-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 8/3115 1/2000 Szymanski-PT-b02-CTLFireability-2024-09 180954 m, 21333 m/sec, 1288796 t fired, .
[lola][.]
[lola][.] Time elapsed: 493 secs. Pages in use: 2
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 28 (type EXCL) for Szymanski-PT-b02-CTLFireability-2024-09
[lola][I] result : true
[lola][I] markings : 205315
[lola][I] fired transitions : 1448783
[lola][I] time used : 9
[lola][I] memory pages used : 2
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Szymanski-PT-b02"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Szymanski-PT-b02, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r401-tall-171690535300858"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Szymanski-PT-b02.tgz
mv Szymanski-PT-b02 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;