fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r401-tall-171690535300850
Last Updated
July 7, 2024

About the Execution of LoLA for Szymanski-PT-a12

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16206.775 1064686.00 1068855.00 2941.90 ?????????????F?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r401-tall-171690535300850.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Szymanski-PT-a12, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r401-tall-171690535300850
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 568K
-rw-r--r-- 1 mcc users 6.6K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K Apr 23 08:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 23 08:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 19 07:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 19:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 11 15:01 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 129K Apr 11 15:01 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.3K Apr 11 15:01 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 83K Apr 11 15:01 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 08:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 23 08:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 101K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-00
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-01
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-02
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-03
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-04
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-05
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-06
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-07
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-08
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-09
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-10
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2024-11
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2023-12
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2023-13
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2023-14
FORMULA_NAME Szymanski-PT-a12-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717181530151

FORMULA Szymanski-PT-a12-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717182594837

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 8 transitions removed,12 places removed
[lola][I] LAUNCH task # 40 (type CNST) for 39 Szymanski-PT-a12-CTLFireability-2023-13
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 40 (type CNST) for Szymanski-PT-a12-CTLFireability-2023-13
[lola][I] result : false
[lola][I] LAUNCH task # 19 (type EXCL) for 18 Szymanski-PT-a12-CTLFireability-2024-06
[lola][I] time limit : 240 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 58 (type EQUN) for 12 Szymanski-PT-a12-CTLFireability-2024-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 59 (type EQUN) for 3 Szymanski-PT-a12-CTLFireability-2024-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 65 (type EQUN) for 12 Szymanski-PT-a12-CTLFireability-2024-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 59 (type EQUN) for Szymanski-PT-a12-CTLFireability-2024-01
[lola][I] result : unknown
[lola][I] LAUNCH task # 63 (type EQUN) for 6 Szymanski-PT-a12-CTLFireability-2024-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 58 (type EQUN) for Szymanski-PT-a12-CTLFireability-2024-04
[lola][I] result : unknown
[lola][I] LAUNCH task # 67 (type EQUN) for 3 Szymanski-PT-a12-CTLFireability-2024-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 67 (type EQUN) for Szymanski-PT-a12-CTLFireability-2024-01
[lola][I] result : unknown
[lola][I] LAUNCH task # 74 (type EQUN) for 0 Szymanski-PT-a12-CTLFireability-2024-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 74 (type EQUN) for Szymanski-PT-a12-CTLFireability-2024-00
[lola][I] result : unknown
[lola][I] LAUNCH task # 71 (type EQUN) for 42 Szymanski-PT-a12-CTLFireability-2023-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 71 (type EQUN) for Szymanski-PT-a12-CTLFireability-2023-14
[lola][I] result : unknown
[lola][I] LAUNCH task # 76 (type EQUN) for 0 Szymanski-PT-a12-CTLFireability-2024-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 76 (type EQUN) for Szymanski-PT-a12-CTLFireability-2024-00
[lola][I] result : unknown
[lola][I] FINISHED task # 65 (type EQUN) for Szymanski-PT-a12-CTLFireability-2024-04
[lola][I] result : unknown
[lola][I] FINISHED task # 63 (type EQUN) for Szymanski-PT-a12-CTLFireability-2024-02
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 5/240 5/2000 Szymanski-PT-a12-CTLFireability-2024-06 1193466 m, 238693 m/sec, 4308056 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 10/240 10/2000 Szymanski-PT-a12-CTLFireability-2024-06 2287239 m, 218754 m/sec, 8489480 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 15/240 14/2000 Szymanski-PT-a12-CTLFireability-2024-06 3342233 m, 210998 m/sec, 12572652 t fired, .
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 14
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 20/240 18/2000 Szymanski-PT-a12-CTLFireability-2024-06 4372500 m, 206053 m/sec, 16589623 t fired, .
[lola][.]
[lola][.] Time elapsed: 20 secs. Pages in use: 18
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 25/240 22/2000 Szymanski-PT-a12-CTLFireability-2024-06 5384118 m, 202323 m/sec, 20556821 t fired, .
[lola][.]
[lola][.] Time elapsed: 25 secs. Pages in use: 22
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 30/240 26/2000 Szymanski-PT-a12-CTLFireability-2024-06 6388307 m, 200837 m/sec, 24514322 t fired, .
[lola][.]
[lola][.] Time elapsed: 30 secs. Pages in use: 26
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 35/240 30/2000 Szymanski-PT-a12-CTLFireability-2024-06 7379564 m, 198251 m/sec, 28426726 t fired, .
[lola][.]
[lola][.] Time elapsed: 35 secs. Pages in use: 30
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 40/240 35/2000 Szymanski-PT-a12-CTLFireability-2024-06 8370875 m, 198262 m/sec, 32360177 t fired, .
[lola][.]
[lola][.] Time elapsed: 40 secs. Pages in use: 35
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 45/240 39/2000 Szymanski-PT-a12-CTLFireability-2024-06 9364714 m, 198767 m/sec, 36297430 t fired, .
[lola][.]
[lola][.] Time elapsed: 45 secs. Pages in use: 39
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 50/240 43/2000 Szymanski-PT-a12-CTLFireability-2024-06 10350087 m, 197074 m/sec, 40212517 t fired, .
[lola][.]
[lola][.] Time elapsed: 50 secs. Pages in use: 43
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 55/240 47/2000 Szymanski-PT-a12-CTLFireability-2024-06 11335761 m, 197134 m/sec, 44124719 t fired, .
[lola][.]
[lola][.] Time elapsed: 55 secs. Pages in use: 47
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 60/240 51/2000 Szymanski-PT-a12-CTLFireability-2024-06 12317504 m, 196348 m/sec, 48035472 t fired, .
[lola][.]
[lola][.] Time elapsed: 60 secs. Pages in use: 51
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 65/240 55/2000 Szymanski-PT-a12-CTLFireability-2024-06 13305624 m, 197624 m/sec, 51963094 t fired, .
[lola][.]
[lola][.] Time elapsed: 65 secs. Pages in use: 55
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 70/240 59/2000 Szymanski-PT-a12-CTLFireability-2024-06 14288354 m, 196546 m/sec, 55889656 t fired, .
[lola][.]
[lola][.] Time elapsed: 70 secs. Pages in use: 59
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 75/240 63/2000 Szymanski-PT-a12-CTLFireability-2024-06 15274858 m, 197300 m/sec, 59838742 t fired, .
[lola][.]
[lola][.] Time elapsed: 75 secs. Pages in use: 63
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 80/240 67/2000 Szymanski-PT-a12-CTLFireability-2024-06 16255037 m, 196035 m/sec, 63805984 t fired, .
[lola][.]
[lola][.] Time elapsed: 80 secs. Pages in use: 67
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 85/240 71/2000 Szymanski-PT-a12-CTLFireability-2024-06 17247488 m, 198490 m/sec, 67817884 t fired, .
[lola][.]
[lola][.] Time elapsed: 85 secs. Pages in use: 71
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 90/240 75/2000 Szymanski-PT-a12-CTLFireability-2024-06 18227197 m, 195941 m/sec, 71866388 t fired, .
[lola][.]
[lola][.] Time elapsed: 90 secs. Pages in use: 75
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 95/240 79/2000 Szymanski-PT-a12-CTLFireability-2024-06 19203655 m, 195291 m/sec, 75970904 t fired, .
[lola][.]
[lola][.] Time elapsed: 95 secs. Pages in use: 79
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 100/240 83/2000 Szymanski-PT-a12-CTLFireability-2024-06 20170393 m, 193347 m/sec, 80054308 t fired, .
[lola][.]
[lola][.] Time elapsed: 100 secs. Pages in use: 83
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 105/240 87/2000 Szymanski-PT-a12-CTLFireability-2024-06 21143111 m, 194543 m/sec, 84192868 t fired, .
[lola][.]
[lola][.] Time elapsed: 105 secs. Pages in use: 87
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 110/240 91/2000 Szymanski-PT-a12-CTLFireability-2024-06 22110477 m, 193473 m/sec, 88350113 t fired, .
[lola][.]
[lola][.] Time elapsed: 110 secs. Pages in use: 91
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 115/240 95/2000 Szymanski-PT-a12-CTLFireability-2024-06 23077789 m, 193462 m/sec, 92555687 t fired, .
[lola][.]
[lola][.] Time elapsed: 115 secs. Pages in use: 95
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 120/240 98/2000 Szymanski-PT-a12-CTLFireability-2024-06 24036453 m, 191732 m/sec, 96773654 t fired, .
[lola][.]
[lola][.] Time elapsed: 120 secs. Pages in use: 98
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 125/240 102/2000 Szymanski-PT-a12-CTLFireability-2024-06 24991721 m, 191053 m/sec, 100971377 t fired, .
[lola][.]
[lola][.] Time elapsed: 125 secs. Pages in use: 102
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 130/240 106/2000 Szymanski-PT-a12-CTLFireability-2024-06 25941584 m, 189972 m/sec, 105189090 t fired, .
[lola][.]
[lola][.] Time elapsed: 130 secs. Pages in use: 106
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 135/240 110/2000 Szymanski-PT-a12-CTLFireability-2024-06 26891668 m, 190016 m/sec, 109420147 t fired, .
[lola][.]
[lola][.] Time elapsed: 135 secs. Pages in use: 110
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 140/240 114/2000 Szymanski-PT-a12-CTLFireability-2024-06 27846788 m, 191024 m/sec, 113683908 t fired, .
[lola][.]
[lola][.] Time elapsed: 140 secs. Pages in use: 114
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 145/240 118/2000 Szymanski-PT-a12-CTLFireability-2024-06 28806308 m, 191904 m/sec, 117961534 t fired, .
[lola][.]
[lola][.] Time elapsed: 145 secs. Pages in use: 118
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 150/240 122/2000 Szymanski-PT-a12-CTLFireability-2024-06 29757454 m, 190229 m/sec, 122266964 t fired, .
[lola][.]
[lola][.] Time elapsed: 150 secs. Pages in use: 122
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 155/240 126/2000 Szymanski-PT-a12-CTLFireability-2024-06 30714994 m, 191508 m/sec, 126588263 t fired, .
[lola][.]
[lola][.] Time elapsed: 155 secs. Pages in use: 126
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 160/240 130/2000 Szymanski-PT-a12-CTLFireability-2024-06 31678458 m, 192692 m/sec, 130912918 t fired, .
[lola][.]
[lola][.] Time elapsed: 160 secs. Pages in use: 130
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 165/240 134/2000 Szymanski-PT-a12-CTLFireability-2024-06 32644568 m, 193222 m/sec, 135253925 t fired, .
[lola][.]
[lola][.] Time elapsed: 165 secs. Pages in use: 134
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 170/240 138/2000 Szymanski-PT-a12-CTLFireability-2024-06 33619791 m, 195044 m/sec, 139640896 t fired, .
[lola][.]
[lola][.] Time elapsed: 170 secs. Pages in use: 138
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 175/240 142/2000 Szymanski-PT-a12-CTLFireability-2024-06 34608311 m, 197704 m/sec, 144063514 t fired, .
[lola][.]
[lola][.] Time elapsed: 175 secs. Pages in use: 142
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 180/240 146/2000 Szymanski-PT-a12-CTLFireability-2024-06 35626082 m, 203554 m/sec, 148566430 t fired, .
[lola][.]
[lola][.] Time elapsed: 180 secs. Pages in use: 146
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 185/240 151/2000 Szymanski-PT-a12-CTLFireability-2024-06 36661505 m, 207084 m/sec, 153212686 t fired, .
[lola][.]
[lola][.] Time elapsed: 185 secs. Pages in use: 151
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 190/240 153/2000 Szymanski-PT-a12-CTLFireability-2024-06 37196379 m, 106974 m/sec, 157057202 t fired, .
[lola][.]
[lola][.] Time elapsed: 190 secs. Pages in use: 153
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 195/240 155/2000 Szymanski-PT-a12-CTLFireability-2024-06 37698006 m, 100325 m/sec, 160768369 t fired, .
[lola][.]
[lola][.] Time elapsed: 195 secs. Pages in use: 155
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 200/240 157/2000 Szymanski-PT-a12-CTLFireability-2024-06 38183417 m, 97082 m/sec, 164407314 t fired, .
[lola][.]
[lola][.] Time elapsed: 200 secs. Pages in use: 157
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 205/240 159/2000 Szymanski-PT-a12-CTLFireability-2024-06 38658254 m, 94967 m/sec, 168011916 t fired, .
[lola][.]
[lola][.] Time elapsed: 205 secs. Pages in use: 159
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 210/240 161/2000 Szymanski-PT-a12-CTLFireability-2024-06 39129309 m, 94211 m/sec, 171592870 t fired, .
[lola][.]
[lola][.] Time elapsed: 210 secs. Pages in use: 161
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 215/240 163/2000 Szymanski-PT-a12-CTLFireability-2024-06 39588124 m, 91763 m/sec, 175109681 t fired, .
[lola][.]
[lola][.] Time elapsed: 215 secs. Pages in use: 163
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 220/240 164/2000 Szymanski-PT-a12-CTLFireability-2024-06 40047955 m, 91966 m/sec, 178638183 t fired, .
[lola][.]
[lola][.] Time elapsed: 220 secs. Pages in use: 164
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 225/240 166/2000 Szymanski-PT-a12-CTLFireability-2024-06 40502082 m, 90825 m/sec, 182121742 t fired, .
[lola][.]
[lola][.] Time elapsed: 225 secs. Pages in use: 166
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 230/240 168/2000 Szymanski-PT-a12-CTLFireability-2024-06 40954515 m, 90486 m/sec, 185588777 t fired, .
[lola][.]
[lola][.] Time elapsed: 230 secs. Pages in use: 168
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 235/240 170/2000 Szymanski-PT-a12-CTLFireability-2024-06 41408469 m, 90790 m/sec, 189066254 t fired, .
[lola][.]
[lola][.] Time elapsed: 235 secs. Pages in use: 170
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 240/240 172/2000 Szymanski-PT-a12-CTLFireability-2024-06 41860163 m, 90338 m/sec, 192529399 t fired, .
[lola][.]
[lola][.] Time elapsed: 240 secs. Pages in use: 172
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][W] CANCELED task # 19 (type EXCL) for Szymanski-PT-a12-CTLFireability-2024-06 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 1 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 245 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 46 (type EXCL) for 45 Szymanski-PT-a12-CTLFireability-2023-15
[lola][I] time limit : 239 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 19 (type EXCL) for 18 Szymanski-PT-a12-CTLFireability-2024-06
[lola][I] time limit : 3355 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 46 (type EXCL) for Szymanski-PT-a12-CTLFireability-2023-15
[lola][I] result : false
[lola][I] markings : 24
[lola][I] fired transitions : 50
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] CANCELED task # 19 (type EXCL) for Szymanski-PT-a12-CTLFireability-2024-06 (memory limit exceeded)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 250 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 37 (type EXCL) for 36 Szymanski-PT-a12-CTLFireability-2023-12
[lola][I] time limit : 257 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 37 (type EXCL) for Szymanski-PT-a12-CTLFireability-2023-12
[lola][I] result : false
[lola][I] markings : 116
[lola][I] fired transitions : 129
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 34 (type EXCL) for 33 Szymanski-PT-a12-CTLFireability-2024-11
[lola][I] time limit : 279 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 34 (type EXCL) for Szymanski-PT-a12-CTLFireability-2024-11
[lola][I] result : false
[lola][I] markings : 116
[lola][I] fired transitions : 457
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 31 (type EXCL) for 30 Szymanski-PT-a12-CTLFireability-2024-10
[lola][I] time limit : 304 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 5/304 5/2000 Szymanski-PT-a12-CTLFireability-2024-10 1218993 m, 243798 m/sec, 4426600 t fired, .
[lola][.]
[lola][.] Time elapsed: 255 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 10/304 10/2000 Szymanski-PT-a12-CTLFireability-2024-10 2295861 m, 215373 m/sec, 8566425 t fired, .
[lola][.]
[lola][.] Time elapsed: 260 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 15/304 14/2000 Szymanski-PT-a12-CTLFireability-2024-10 3333130 m, 207453 m/sec, 12607462 t fired, .
[lola][.]
[lola][.] Time elapsed: 265 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 20/304 18/2000 Szymanski-PT-a12-CTLFireability-2024-10 4322389 m, 197851 m/sec, 16493338 t fired, .
[lola][.]
[lola][.] Time elapsed: 270 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 25/304 22/2000 Szymanski-PT-a12-CTLFireability-2024-10 5270375 m, 189597 m/sec, 20238649 t fired, .
[lola][.]
[lola][.] Time elapsed: 275 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 30/304 26/2000 Szymanski-PT-a12-CTLFireability-2024-10 6211681 m, 188261 m/sec, 23975144 t fired, .
[lola][.]
[lola][.] Time elapsed: 280 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 35/304 30/2000 Szymanski-PT-a12-CTLFireability-2024-10 7142891 m, 186242 m/sec, 27688644 t fired, .
[lola][.]
[lola][.] Time elapsed: 285 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 40/304 33/2000 Szymanski-PT-a12-CTLFireability-2024-10 8066853 m, 184792 m/sec, 31399069 t fired, .
[lola][.]
[lola][.] Time elapsed: 290 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 45/304 37/2000 Szymanski-PT-a12-CTLFireability-2024-10 8993168 m, 185263 m/sec, 35098728 t fired, .
[lola][.]
[lola][.] Time elapsed: 295 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 50/304 41/2000 Szymanski-PT-a12-CTLFireability-2024-10 9912530 m, 183872 m/sec, 38799986 t fired, .
[lola][.]
[lola][.] Time elapsed: 300 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 55/304 45/2000 Szymanski-PT-a12-CTLFireability-2024-10 10827425 m, 182979 m/sec, 42484699 t fired, .
[lola][.]
[lola][.] Time elapsed: 305 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 60/304 48/2000 Szymanski-PT-a12-CTLFireability-2024-10 11738329 m, 182180 m/sec, 46169900 t fired, .
[lola][.]
[lola][.] Time elapsed: 310 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 65/304 52/2000 Szymanski-PT-a12-CTLFireability-2024-10 12645555 m, 181445 m/sec, 49850246 t fired, .
[lola][.]
[lola][.] Time elapsed: 315 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 70/304 56/2000 Szymanski-PT-a12-CTLFireability-2024-10 13558343 m, 182557 m/sec, 53541287 t fired, .
[lola][.]
[lola][.] Time elapsed: 320 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 75/304 59/2000 Szymanski-PT-a12-CTLFireability-2024-10 14468003 m, 181932 m/sec, 57254592 t fired, .
[lola][.]
[lola][.] Time elapsed: 325 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 80/304 63/2000 Szymanski-PT-a12-CTLFireability-2024-10 15376935 m, 181786 m/sec, 60993996 t fired, .
[lola][.]
[lola][.] Time elapsed: 330 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 85/304 67/2000 Szymanski-PT-a12-CTLFireability-2024-10 16278439 m, 180300 m/sec, 64739842 t fired, .
[lola][.]
[lola][.] Time elapsed: 335 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 90/304 70/2000 Szymanski-PT-a12-CTLFireability-2024-10 17185769 m, 181466 m/sec, 68526395 t fired, .
[lola][.]
[lola][.] Time elapsed: 340 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 95/304 74/2000 Szymanski-PT-a12-CTLFireability-2024-10 18079906 m, 178827 m/sec, 72355340 t fired, .
[lola][.]
[lola][.] Time elapsed: 345 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 100/304 78/2000 Szymanski-PT-a12-CTLFireability-2024-10 18971239 m, 178266 m/sec, 76220393 t fired, .
[lola][.]
[lola][.] Time elapsed: 350 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 105/304 81/2000 Szymanski-PT-a12-CTLFireability-2024-10 19850632 m, 175878 m/sec, 80112922 t fired, .
[lola][.]
[lola][.] Time elapsed: 355 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 110/304 85/2000 Szymanski-PT-a12-CTLFireability-2024-10 20728974 m, 175668 m/sec, 84034469 t fired, .
[lola][.]
[lola][.] Time elapsed: 360 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 115/304 89/2000 Szymanski-PT-a12-CTLFireability-2024-10 21604730 m, 175151 m/sec, 87965867 t fired, .
[lola][.]
[lola][.] Time elapsed: 365 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 120/304 92/2000 Szymanski-PT-a12-CTLFireability-2024-10 22475232 m, 174100 m/sec, 91903634 t fired, .
[lola][.]
[lola][.] Time elapsed: 370 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 125/304 96/2000 Szymanski-PT-a12-CTLFireability-2024-10 23344046 m, 173762 m/sec, 95875963 t fired, .
[lola][.]
[lola][.] Time elapsed: 375 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 130/304 99/2000 Szymanski-PT-a12-CTLFireability-2024-10 24202132 m, 171617 m/sec, 99880912 t fired, .
[lola][.]
[lola][.] Time elapsed: 380 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 135/304 103/2000 Szymanski-PT-a12-CTLFireability-2024-10 25065467 m, 172667 m/sec, 103880001 t fired, .
[lola][.]
[lola][.] Time elapsed: 385 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 140/304 106/2000 Szymanski-PT-a12-CTLFireability-2024-10 25920624 m, 171031 m/sec, 107903150 t fired, .
[lola][.]
[lola][.] Time elapsed: 390 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 145/304 110/2000 Szymanski-PT-a12-CTLFireability-2024-10 26774401 m, 170755 m/sec, 111934294 t fired, .
[lola][.]
[lola][.] Time elapsed: 395 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 150/304 113/2000 Szymanski-PT-a12-CTLFireability-2024-10 27628980 m, 170915 m/sec, 115953034 t fired, .
[lola][.]
[lola][.] Time elapsed: 400 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 155/304 117/2000 Szymanski-PT-a12-CTLFireability-2024-10 28481153 m, 170434 m/sec, 120005821 t fired, .
[lola][.]
[lola][.] Time elapsed: 405 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 160/304 120/2000 Szymanski-PT-a12-CTLFireability-2024-10 29330065 m, 169782 m/sec, 124076905 t fired, .
[lola][.]
[lola][.] Time elapsed: 410 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 165/304 124/2000 Szymanski-PT-a12-CTLFireability-2024-10 30182295 m, 170446 m/sec, 128172256 t fired, .
[lola][.]
[lola][.] Time elapsed: 415 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 170/304 127/2000 Szymanski-PT-a12-CTLFireability-2024-10 31029877 m, 169516 m/sec, 132259015 t fired, .
[lola][.]
[lola][.] Time elapsed: 420 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 175/304 131/2000 Szymanski-PT-a12-CTLFireability-2024-10 31889885 m, 172001 m/sec, 136342342 t fired, .
[lola][.]
[lola][.] Time elapsed: 425 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 180/304 134/2000 Szymanski-PT-a12-CTLFireability-2024-10 32743377 m, 170698 m/sec, 140472634 t fired, .
[lola][.]
[lola][.] Time elapsed: 430 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 185/304 138/2000 Szymanski-PT-a12-CTLFireability-2024-10 33601234 m, 171571 m/sec, 144611286 t fired, .
[lola][.]
[lola][.] Time elapsed: 435 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 190/304 141/2000 Szymanski-PT-a12-CTLFireability-2024-10 34472532 m, 174259 m/sec, 148794073 t fired, .
[lola][.]
[lola][.] Time elapsed: 440 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 195/304 145/2000 Szymanski-PT-a12-CTLFireability-2024-10 35353561 m, 176205 m/sec, 153026756 t fired, .
[lola][.]
[lola][.] Time elapsed: 445 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 200/304 149/2000 Szymanski-PT-a12-CTLFireability-2024-10 36274306 m, 184149 m/sec, 157386495 t fired, .
[lola][.]
[lola][.] Time elapsed: 450 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 205/304 152/2000 Szymanski-PT-a12-CTLFireability-2024-10 36924440 m, 130026 m/sec, 161577432 t fired, .
[lola][.]
[lola][.] Time elapsed: 455 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 210/304 154/2000 Szymanski-PT-a12-CTLFireability-2024-10 37382000 m, 91512 m/sec, 165370921 t fired, .
[lola][.]
[lola][.] Time elapsed: 460 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 215/304 155/2000 Szymanski-PT-a12-CTLFireability-2024-10 37816132 m, 86826 m/sec, 169048962 t fired, .
[lola][.]
[lola][.] Time elapsed: 465 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 220/304 157/2000 Szymanski-PT-a12-CTLFireability-2024-10 38243689 m, 85511 m/sec, 172683968 t fired, .
[lola][.]
[lola][.] Time elapsed: 470 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 225/304 159/2000 Szymanski-PT-a12-CTLFireability-2024-10 38667402 m, 84742 m/sec, 176322416 t fired, .
[lola][.]
[lola][.] Time elapsed: 475 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 230/304 161/2000 Szymanski-PT-a12-CTLFireability-2024-10 39085163 m, 83552 m/sec, 179916214 t fired, .
[lola][.]
[lola][.] Time elapsed: 480 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 235/304 162/2000 Szymanski-PT-a12-CTLFireability-2024-10 39500644 m, 83096 m/sec, 183513113 t fired, .
[lola][.]
[lola][.] Time elapsed: 485 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 240/304 164/2000 Szymanski-PT-a12-CTLFireability-2024-10 39913362 m, 82543 m/sec, 187094216 t fired, .
[lola][.]
[lola][.] Time elapsed: 490 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 245/304 166/2000 Szymanski-PT-a12-CTLFireability-2024-10 40325236 m, 82374 m/sec, 190669440 t fired, .
[lola][.]
[lola][.] Time elapsed: 495 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 250/304 167/2000 Szymanski-PT-a12-CTLFireability-2024-10 40738487 m, 82650 m/sec, 194248029 t fired, .
[lola][.]
[lola][.] Time elapsed: 500 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 255/304 169/2000 Szymanski-PT-a12-CTLFireability-2024-10 41150612 m, 82425 m/sec, 197807646 t fired, .
[lola][.]
[lola][.] Time elapsed: 505 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 260/304 171/2000 Szymanski-PT-a12-CTLFireability-2024-10 41561749 m, 82227 m/sec, 201369830 t fired, .
[lola][.]
[lola][.] Time elapsed: 510 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 265/304 172/2000 Szymanski-PT-a12-CTLFireability-2024-10 41971505 m, 81951 m/sec, 204924675 t fired, .
[lola][.]
[lola][.] Time elapsed: 515 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 270/304 174/2000 Szymanski-PT-a12-CTLFireability-2024-10 42383663 m, 82431 m/sec, 208493671 t fired, .
[lola][.]
[lola][.] Time elapsed: 520 secs. Pages in use: 174
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 275/304 176/2000 Szymanski-PT-a12-CTLFireability-2024-10 42793611 m, 81989 m/sec, 212016356 t fired, .
[lola][.]
[lola][.] Time elapsed: 525 secs. Pages in use: 176
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 280/304 177/2000 Szymanski-PT-a12-CTLFireability-2024-10 43204515 m, 82180 m/sec, 215572879 t fired, .
[lola][.]
[lola][.] Time elapsed: 530 secs. Pages in use: 177
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 285/304 179/2000 Szymanski-PT-a12-CTLFireability-2024-10 43616932 m, 82483 m/sec, 219126246 t fired, .
[lola][.]
[lola][.] Time elapsed: 535 secs. Pages in use: 179
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 290/304 181/2000 Szymanski-PT-a12-CTLFireability-2024-10 44025612 m, 81736 m/sec, 222653430 t fired, .
[lola][.]
[lola][.] Time elapsed: 540 secs. Pages in use: 181
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 295/304 182/2000 Szymanski-PT-a12-CTLFireability-2024-10 44434628 m, 81803 m/sec, 226168505 t fired, .
[lola][.]
[lola][.] Time elapsed: 545 secs. Pages in use: 182
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 300/304 184/2000 Szymanski-PT-a12-CTLFireability-2024-10 44840619 m, 81198 m/sec, 229647772 t fired, .
[lola][.]
[lola][.] Time elapsed: 550 secs. Pages in use: 184
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][W] CANCELED task # 31 (type EXCL) for Szymanski-PT-a12-CTLFireability-2024-10 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 1 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 555 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 28 (type EXCL) for 27 Szymanski-PT-a12-CTLFireability-2024-09
[lola][I] time limit : 304 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 31 (type EXCL) for 30 Szymanski-PT-a12-CTLFireability-2024-10
[lola][I] time limit : 3045 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 28 (type EXCL) for Szymanski-PT-a12-CTLFireability-2024-09
[lola][I] result : true
[lola][I] markings : 116
[lola][I] fired transitions : 128
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 CTL EXCL 5/304 5/5 Szymanski-PT-a12-CTLFireability-2024-10 1206789 m, -8726766 m/sec, 4379622 t fired, .
[lola][.]
[lola][.] Time elapsed: 560 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] CANCELED task # 31 (type EXCL) for Szymanski-PT-a12-CTLFireability-2024-10 (memory limit exceeded)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 565 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 22 (type EXCL) for 21 Szymanski-PT-a12-CTLFireability-2024-07
[lola][I] time limit : 337 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 22 (type EXCL) for Szymanski-PT-a12-CTLFireability-2024-07
[lola][I] result : true
[lola][I] markings : 289
[lola][I] fired transitions : 593
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 16 (type EXCL) for 15 Szymanski-PT-a12-CTLFireability-2024-05
[lola][I] time limit : 379 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 5/379 6/2000 Szymanski-PT-a12-CTLFireability-2024-05 1320490 m, 264098 m/sec, 4790379 t fired, .
[lola][.]
[lola][.] Time elapsed: 570 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 10/379 11/2000 Szymanski-PT-a12-CTLFireability-2024-05 2475049 m, 230911 m/sec, 9210818 t fired, .
[lola][.]
[lola][.] Time elapsed: 575 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 15/379 15/2000 Szymanski-PT-a12-CTLFireability-2024-05 3578618 m, 220713 m/sec, 13487213 t fired, .
[lola][.]
[lola][.] Time elapsed: 580 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 20/379 19/2000 Szymanski-PT-a12-CTLFireability-2024-05 4619759 m, 208228 m/sec, 17560093 t fired, .
[lola][.]
[lola][.] Time elapsed: 585 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 25/379 23/2000 Szymanski-PT-a12-CTLFireability-2024-05 5650269 m, 206102 m/sec, 21600442 t fired, .
[lola][.]
[lola][.] Time elapsed: 590 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 30/379 28/2000 Szymanski-PT-a12-CTLFireability-2024-05 6663479 m, 202642 m/sec, 25599749 t fired, .
[lola][.]
[lola][.] Time elapsed: 595 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 35/379 32/2000 Szymanski-PT-a12-CTLFireability-2024-05 7670595 m, 201423 m/sec, 29583761 t fired, .
[lola][.]
[lola][.] Time elapsed: 600 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 40/379 36/2000 Szymanski-PT-a12-CTLFireability-2024-05 8677844 m, 201449 m/sec, 33564614 t fired, .
[lola][.]
[lola][.] Time elapsed: 605 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 45/379 40/2000 Szymanski-PT-a12-CTLFireability-2024-05 9674530 m, 199337 m/sec, 37524558 t fired, .
[lola][.]
[lola][.] Time elapsed: 610 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 50/379 44/2000 Szymanski-PT-a12-CTLFireability-2024-05 10674717 m, 200037 m/sec, 41497197 t fired, .
[lola][.]
[lola][.] Time elapsed: 615 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 55/379 48/2000 Szymanski-PT-a12-CTLFireability-2024-05 11668519 m, 198760 m/sec, 45453016 t fired, .
[lola][.]
[lola][.] Time elapsed: 620 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 60/379 52/2000 Szymanski-PT-a12-CTLFireability-2024-05 12662763 m, 198848 m/sec, 49418820 t fired, .
[lola][.]
[lola][.] Time elapsed: 625 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 65/379 56/2000 Szymanski-PT-a12-CTLFireability-2024-05 13659253 m, 199298 m/sec, 53374099 t fired, .
[lola][.]
[lola][.] Time elapsed: 630 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 70/379 60/2000 Szymanski-PT-a12-CTLFireability-2024-05 14652590 m, 198667 m/sec, 57339051 t fired, .
[lola][.]
[lola][.] Time elapsed: 635 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 75/379 64/2000 Szymanski-PT-a12-CTLFireability-2024-05 15643879 m, 198257 m/sec, 61328787 t fired, .
[lola][.]
[lola][.] Time elapsed: 640 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 80/379 68/2000 Szymanski-PT-a12-CTLFireability-2024-05 16635552 m, 198334 m/sec, 65344693 t fired, .
[lola][.]
[lola][.] Time elapsed: 645 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 85/379 72/2000 Szymanski-PT-a12-CTLFireability-2024-05 17631097 m, 199109 m/sec, 69404762 t fired, .
[lola][.]
[lola][.] Time elapsed: 650 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 90/379 76/2000 Szymanski-PT-a12-CTLFireability-2024-05 18621109 m, 198002 m/sec, 73504845 t fired, .
[lola][.]
[lola][.] Time elapsed: 655 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 95/379 80/2000 Szymanski-PT-a12-CTLFireability-2024-05 19602938 m, 196365 m/sec, 77659706 t fired, .
[lola][.]
[lola][.] Time elapsed: 660 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 100/379 84/2000 Szymanski-PT-a12-CTLFireability-2024-05 20582164 m, 195845 m/sec, 81804872 t fired, .
[lola][.]
[lola][.] Time elapsed: 665 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 105/379 88/2000 Szymanski-PT-a12-CTLFireability-2024-05 21560201 m, 195607 m/sec, 85998870 t fired, .
[lola][.]
[lola][.] Time elapsed: 670 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 110/379 92/2000 Szymanski-PT-a12-CTLFireability-2024-05 22531318 m, 194223 m/sec, 90175457 t fired, .
[lola][.]
[lola][.] Time elapsed: 675 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 115/379 96/2000 Szymanski-PT-a12-CTLFireability-2024-05 23496971 m, 193130 m/sec, 94399813 t fired, .
[lola][.]
[lola][.] Time elapsed: 680 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 120/379 100/2000 Szymanski-PT-a12-CTLFireability-2024-05 24464442 m, 193494 m/sec, 98648665 t fired, .
[lola][.]
[lola][.] Time elapsed: 685 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 125/379 104/2000 Szymanski-PT-a12-CTLFireability-2024-05 25422962 m, 191704 m/sec, 102897277 t fired, .
[lola][.]
[lola][.] Time elapsed: 690 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 130/379 108/2000 Szymanski-PT-a12-CTLFireability-2024-05 26383058 m, 192019 m/sec, 107163056 t fired, .
[lola][.]
[lola][.] Time elapsed: 695 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 135/379 112/2000 Szymanski-PT-a12-CTLFireability-2024-05 27344201 m, 192228 m/sec, 111429274 t fired, .
[lola][.]
[lola][.] Time elapsed: 700 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 140/379 116/2000 Szymanski-PT-a12-CTLFireability-2024-05 28301850 m, 191529 m/sec, 115718737 t fired, .
[lola][.]
[lola][.] Time elapsed: 705 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 145/379 120/2000 Szymanski-PT-a12-CTLFireability-2024-05 29260088 m, 191647 m/sec, 120026594 t fired, .
[lola][.]
[lola][.] Time elapsed: 710 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 150/379 124/2000 Szymanski-PT-a12-CTLFireability-2024-05 30222629 m, 192508 m/sec, 124362911 t fired, .
[lola][.]
[lola][.] Time elapsed: 715 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 155/379 128/2000 Szymanski-PT-a12-CTLFireability-2024-05 31183587 m, 192191 m/sec, 128710048 t fired, .
[lola][.]
[lola][.] Time elapsed: 720 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 160/379 132/2000 Szymanski-PT-a12-CTLFireability-2024-05 32155020 m, 194286 m/sec, 133036377 t fired, .
[lola][.]
[lola][.] Time elapsed: 725 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 165/379 136/2000 Szymanski-PT-a12-CTLFireability-2024-05 33125075 m, 194011 m/sec, 137422875 t fired, .
[lola][.]
[lola][.] Time elapsed: 730 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 170/379 140/2000 Szymanski-PT-a12-CTLFireability-2024-05 34109675 m, 196920 m/sec, 141821902 t fired, .
[lola][.]
[lola][.] Time elapsed: 735 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 175/379 144/2000 Szymanski-PT-a12-CTLFireability-2024-05 35107373 m, 199539 m/sec, 146278244 t fired, .
[lola][.]
[lola][.] Time elapsed: 740 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 180/379 148/2000 Szymanski-PT-a12-CTLFireability-2024-05 36151840 m, 208893 m/sec, 150841783 t fired, .
[lola][.]
[lola][.] Time elapsed: 745 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 185/379 152/2000 Szymanski-PT-a12-CTLFireability-2024-05 36925869 m, 154805 m/sec, 155083980 t fired, .
[lola][.]
[lola][.] Time elapsed: 750 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 190/379 154/2000 Szymanski-PT-a12-CTLFireability-2024-05 37434578 m, 101741 m/sec, 158793466 t fired, .
[lola][.]
[lola][.] Time elapsed: 755 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 195/379 156/2000 Szymanski-PT-a12-CTLFireability-2024-05 37917346 m, 96553 m/sec, 162417623 t fired, .
[lola][.]
[lola][.] Time elapsed: 760 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 200/379 158/2000 Szymanski-PT-a12-CTLFireability-2024-05 38392589 m, 95048 m/sec, 165984381 t fired, .
[lola][.]
[lola][.] Time elapsed: 765 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 205/379 160/2000 Szymanski-PT-a12-CTLFireability-2024-05 38862341 m, 93950 m/sec, 169555574 t fired, .
[lola][.]
[lola][.] Time elapsed: 770 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 210/379 162/2000 Szymanski-PT-a12-CTLFireability-2024-05 39322315 m, 91994 m/sec, 173074437 t fired, .
[lola][.]
[lola][.] Time elapsed: 775 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 215/379 163/2000 Szymanski-PT-a12-CTLFireability-2024-05 39782820 m, 92101 m/sec, 176603055 t fired, .
[lola][.]
[lola][.] Time elapsed: 780 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 220/379 165/2000 Szymanski-PT-a12-CTLFireability-2024-05 40237260 m, 90888 m/sec, 180093223 t fired, .
[lola][.]
[lola][.] Time elapsed: 785 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 225/379 167/2000 Szymanski-PT-a12-CTLFireability-2024-05 40690012 m, 90550 m/sec, 183563040 t fired, .
[lola][.]
[lola][.] Time elapsed: 790 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 230/379 169/2000 Szymanski-PT-a12-CTLFireability-2024-05 41143832 m, 90764 m/sec, 187030026 t fired, .
[lola][.]
[lola][.] Time elapsed: 795 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 235/379 171/2000 Szymanski-PT-a12-CTLFireability-2024-05 41597491 m, 90731 m/sec, 190509921 t fired, .
[lola][.]
[lola][.] Time elapsed: 800 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 240/379 173/2000 Szymanski-PT-a12-CTLFireability-2024-05 42049416 m, 90385 m/sec, 193971733 t fired, .
[lola][.]
[lola][.] Time elapsed: 805 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 245/379 175/2000 Szymanski-PT-a12-CTLFireability-2024-05 42507315 m, 91579 m/sec, 197479934 t fired, .
[lola][.]
[lola][.] Time elapsed: 810 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 250/379 176/2000 Szymanski-PT-a12-CTLFireability-2024-05 42964392 m, 91415 m/sec, 200964986 t fired, .
[lola][.]
[lola][.] Time elapsed: 815 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 255/379 178/2000 Szymanski-PT-a12-CTLFireability-2024-05 43422921 m, 91705 m/sec, 204456367 t fired, .
[lola][.]
[lola][.] Time elapsed: 820 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 260/379 180/2000 Szymanski-PT-a12-CTLFireability-2024-05 43877333 m, 90882 m/sec, 207926221 t fired, .
[lola][.]
[lola][.] Time elapsed: 825 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 265/379 182/2000 Szymanski-PT-a12-CTLFireability-2024-05 44329337 m, 90400 m/sec, 211359986 t fired, .
[lola][.]
[lola][.] Time elapsed: 830 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 270/379 184/2000 Szymanski-PT-a12-CTLFireability-2024-05 44783587 m, 90850 m/sec, 214805986 t fired, .
[lola][.]
[lola][.] Time elapsed: 835 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 275/379 186/2000 Szymanski-PT-a12-CTLFireability-2024-05 45236724 m, 90627 m/sec, 218256402 t fired, .
[lola][.]
[lola][.] Time elapsed: 840 secs. Pages in use: 186
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 280/379 187/2000 Szymanski-PT-a12-CTLFireability-2024-05 45689685 m, 90592 m/sec, 221676564 t fired, .
[lola][.]
[lola][.] Time elapsed: 845 secs. Pages in use: 187
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 285/379 189/2000 Szymanski-PT-a12-CTLFireability-2024-05 46141578 m, 90378 m/sec, 225094809 t fired, .
[lola][.]
[lola][.] Time elapsed: 850 secs. Pages in use: 189
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 290/379 191/2000 Szymanski-PT-a12-CTLFireability-2024-05 46594543 m, 90593 m/sec, 228494645 t fired, .
[lola][.]
[lola][.] Time elapsed: 855 secs. Pages in use: 191
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 295/379 193/2000 Szymanski-PT-a12-CTLFireability-2024-05 47044793 m, 90050 m/sec, 231880067 t fired, .
[lola][.]
[lola][.] Time elapsed: 860 secs. Pages in use: 193
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 300/379 195/2000 Szymanski-PT-a12-CTLFireability-2024-05 47496374 m, 90316 m/sec, 235275334 t fired, .
[lola][.]
[lola][.] Time elapsed: 865 secs. Pages in use: 195
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 305/379 197/2000 Szymanski-PT-a12-CTLFireability-2024-05 47944691 m, 89663 m/sec, 238651470 t fired, .
[lola][.]
[lola][.] Time elapsed: 870 secs. Pages in use: 197
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 310/379 199/2000 Szymanski-PT-a12-CTLFireability-2024-05 48401059 m, 91273 m/sec, 242055101 t fired, .
[lola][.]
[lola][.] Time elapsed: 875 secs. Pages in use: 199
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 315/379 200/2000 Szymanski-PT-a12-CTLFireability-2024-05 48854924 m, 90773 m/sec, 245445581 t fired, .
[lola][.]
[lola][.] Time elapsed: 880 secs. Pages in use: 200
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 320/379 202/2000 Szymanski-PT-a12-CTLFireability-2024-05 49312396 m, 91494 m/sec, 248832939 t fired, .
[lola][.]
[lola][.] Time elapsed: 885 secs. Pages in use: 202
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 325/379 204/2000 Szymanski-PT-a12-CTLFireability-2024-05 49769321 m, 91385 m/sec, 252199474 t fired, .
[lola][.]
[lola][.] Time elapsed: 890 secs. Pages in use: 204
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 330/379 206/2000 Szymanski-PT-a12-CTLFireability-2024-05 50223992 m, 90934 m/sec, 255570448 t fired, .
[lola][.]
[lola][.] Time elapsed: 895 secs. Pages in use: 206
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 335/379 208/2000 Szymanski-PT-a12-CTLFireability-2024-05 50679237 m, 91049 m/sec, 258937665 t fired, .
[lola][.]
[lola][.] Time elapsed: 900 secs. Pages in use: 208
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 340/379 210/2000 Szymanski-PT-a12-CTLFireability-2024-05 51133521 m, 90856 m/sec, 262266792 t fired, .
[lola][.]
[lola][.] Time elapsed: 905 secs. Pages in use: 210
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 345/379 211/2000 Szymanski-PT-a12-CTLFireability-2024-05 51585116 m, 90319 m/sec, 265594278 t fired, .
[lola][.]
[lola][.] Time elapsed: 910 secs. Pages in use: 211
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 350/379 213/2000 Szymanski-PT-a12-CTLFireability-2024-05 52035311 m, 90039 m/sec, 268915442 t fired, .
[lola][.]
[lola][.] Time elapsed: 915 secs. Pages in use: 213
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 355/379 215/2000 Szymanski-PT-a12-CTLFireability-2024-05 52488494 m, 90636 m/sec, 272233703 t fired, .
[lola][.]
[lola][.] Time elapsed: 920 secs. Pages in use: 215
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 360/379 217/2000 Szymanski-PT-a12-CTLFireability-2024-05 52936976 m, 89696 m/sec, 275523809 t fired, .
[lola][.]
[lola][.] Time elapsed: 925 secs. Pages in use: 217
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 365/379 219/2000 Szymanski-PT-a12-CTLFireability-2024-05 53390205 m, 90645 m/sec, 278832896 t fired, .
[lola][.]
[lola][.] Time elapsed: 930 secs. Pages in use: 219
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 370/379 221/2000 Szymanski-PT-a12-CTLFireability-2024-05 53841839 m, 90326 m/sec, 282114036 t fired, .
[lola][.]
[lola][.] Time elapsed: 935 secs. Pages in use: 221
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 375/379 222/2000 Szymanski-PT-a12-CTLFireability-2024-05 54294154 m, 90463 m/sec, 285394185 t fired, .
[lola][.]
[lola][.] Time elapsed: 940 secs. Pages in use: 222
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][W] CANCELED task # 16 (type EXCL) for Szymanski-PT-a12-CTLFireability-2024-05 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 1 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 945 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 10 (type EXCL) for 9 Szymanski-PT-a12-CTLFireability-2024-03
[lola][I] time limit : 379 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 16 (type EXCL) for 15 Szymanski-PT-a12-CTLFireability-2024-05
[lola][I] time limit : 2655 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 10 (type EXCL) for Szymanski-PT-a12-CTLFireability-2024-03
[lola][I] result : true
[lola][I] markings : 116
[lola][I] fired transitions : 128
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] CANCELED task # 16 (type EXCL) for Szymanski-PT-a12-CTLFireability-2024-05 (memory limit exceeded)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 950 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 70 (type EXCL) for 0 Szymanski-PT-a12-CTLFireability-2024-00
[lola][I] time limit : 441 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 5/441 6/2000 Szymanski-PT-a12-CTLFireability-2024-00 1445120 m, 289024 m/sec, 5266623 t fired, .
[lola][.]
[lola][.] Time elapsed: 955 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 10/441 10/2000 Szymanski-PT-a12-CTLFireability-2024-00 2711060 m, 253188 m/sec, 10123297 t fired, .
[lola][.]
[lola][.] Time elapsed: 960 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 15/441 15/2000 Szymanski-PT-a12-CTLFireability-2024-00 3931687 m, 244125 m/sec, 14864205 t fired, .
[lola][.]
[lola][.] Time elapsed: 965 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 20/441 19/2000 Szymanski-PT-a12-CTLFireability-2024-00 5122107 m, 238084 m/sec, 19532920 t fired, .
[lola][.]
[lola][.] Time elapsed: 970 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 25/441 24/2000 Szymanski-PT-a12-CTLFireability-2024-00 6289628 m, 233504 m/sec, 24124238 t fired, .
[lola][.]
[lola][.] Time elapsed: 975 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 30/441 28/2000 Szymanski-PT-a12-CTLFireability-2024-00 7451693 m, 232413 m/sec, 28709738 t fired, .
[lola][.]
[lola][.] Time elapsed: 980 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 35/441 32/2000 Szymanski-PT-a12-CTLFireability-2024-00 8597338 m, 229129 m/sec, 33250463 t fired, .
[lola][.]
[lola][.] Time elapsed: 985 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 40/441 36/2000 Szymanski-PT-a12-CTLFireability-2024-00 9716140 m, 223760 m/sec, 37689881 t fired, .
[lola][.]
[lola][.] Time elapsed: 990 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 45/441 40/2000 Szymanski-PT-a12-CTLFireability-2024-00 10831241 m, 223020 m/sec, 42121584 t fired, .
[lola][.]
[lola][.] Time elapsed: 995 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 50/441 44/2000 Szymanski-PT-a12-CTLFireability-2024-00 11934470 m, 220645 m/sec, 46509152 t fired, .
[lola][.]
[lola][.] Time elapsed: 1000 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 55/441 49/2000 Szymanski-PT-a12-CTLFireability-2024-00 13039646 m, 221035 m/sec, 50908063 t fired, .
[lola][.]
[lola][.] Time elapsed: 1005 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 60/441 53/2000 Szymanski-PT-a12-CTLFireability-2024-00 14143178 m, 220706 m/sec, 55313880 t fired, .
[lola][.]
[lola][.] Time elapsed: 1010 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 65/441 57/2000 Szymanski-PT-a12-CTLFireability-2024-00 15249752 m, 221314 m/sec, 59736753 t fired, .
[lola][.]
[lola][.] Time elapsed: 1015 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 70/441 61/2000 Szymanski-PT-a12-CTLFireability-2024-00 16349684 m, 219986 m/sec, 64186324 t fired, .
[lola][.]
[lola][.] Time elapsed: 1020 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 75/441 65/2000 Szymanski-PT-a12-CTLFireability-2024-00 17452785 m, 220620 m/sec, 68669319 t fired, .
[lola][.]
[lola][.] Time elapsed: 1025 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 80/441 69/2000 Szymanski-PT-a12-CTLFireability-2024-00 18543524 m, 218147 m/sec, 73188626 t fired, .
[lola][.]
[lola][.] Time elapsed: 1030 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 85/441 73/2000 Szymanski-PT-a12-CTLFireability-2024-00 19626198 m, 216534 m/sec, 77756626 t fired, .
[lola][.]
[lola][.] Time elapsed: 1035 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 90/441 77/2000 Szymanski-PT-a12-CTLFireability-2024-00 20704458 m, 215652 m/sec, 82334927 t fired, .
[lola][.]
[lola][.] Time elapsed: 1040 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 95/441 81/2000 Szymanski-PT-a12-CTLFireability-2024-00 21779471 m, 215002 m/sec, 86938096 t fired, .
[lola][.]
[lola][.] Time elapsed: 1045 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 100/441 85/2000 Szymanski-PT-a12-CTLFireability-2024-00 22847328 m, 213571 m/sec, 91559111 t fired, .
[lola][.]
[lola][.] Time elapsed: 1050 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 105/441 89/2000 Szymanski-PT-a12-CTLFireability-2024-00 23907795 m, 212093 m/sec, 96204024 t fired, .
[lola][.]
[lola][.] Time elapsed: 1055 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] Szymanski-PT-a12-CTLFireability-2024-03: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] Szymanski-PT-a12-CTLFireability-2023-13: INITIAL false preprocessing
[lola][.] Szymanski-PT-a12-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] Szymanski-PT-a12-CTLFireability-2024-00: EFAG 0 0 1 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-04: AGEF 0 1 0 0 3 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] Szymanski-PT-a12-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[lola][.] Szymanski-PT-a12-CTLFireability-2023-14: EG 0 1 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 70 AGEF EXCL 110/441 93/2000 Szymanski-PT-a12-CTLFireability-2024-00 24965459 m, 211532 m/sec, 100860117 t fired, .
[lola][.]
[lola][.] Time elapsed: 1060 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 411 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Szymanski-PT-a12"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Szymanski-PT-a12, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r401-tall-171690535300850"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Szymanski-PT-a12.tgz
mv Szymanski-PT-a12 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;