About the Execution of LoLA for Szymanski-PT-a08
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16205.600 | 360460.00 | 510756.00 | 1942.50 | ??FF???????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r401-tall-171690535300834.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Szymanski-PT-a08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r401-tall-171690535300834
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 488K
-rw-r--r-- 1 mcc users 6.6K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Apr 23 08:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 08:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 19 19:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.4K Apr 11 14:58 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 75K Apr 11 14:58 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Apr 11 14:57 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Apr 11 14:57 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 08:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 23 08:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 101K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-00
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-01
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-02
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-03
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-04
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-05
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-06
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-07
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-08
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-09
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-10
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2024-11
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2023-12
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2023-13
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2023-14
FORMULA_NAME Szymanski-PT-a08-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717179693170
FORMULA Szymanski-PT-a08-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Szymanski-PT-a08-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717180053630
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 8 transitions removed,12 places removed
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 Szymanski-PT-a08-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 116 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for Szymanski-PT-a08-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 141
[[35mlola[0m][I] fired transitions : 641
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 Szymanski-PT-a08-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 120 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 30 Szymanski-PT-a08-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 75 (type EQUN) for 30 Szymanski-PT-a08-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 79 (type EQUN) for 57 Szymanski-PT-a08-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 7 (type CNST) for 6 Szymanski-PT-a08-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 7 (type CNST) for Szymanski-PT-a08-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 73 (type EQUN) for Szymanski-PT-a08-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 79 (type EQUN) for Szymanski-PT-a08-CTLFireability-2023-15
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 75 (type EQUN) for Szymanski-PT-a08-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/200 5/2000 Szymanski-PT-a08-CTLFireability-2024-01 1107305 m, 221461 m/sec, 4339390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/200 9/2000 Szymanski-PT-a08-CTLFireability-2024-01 2157394 m, 210017 m/sec, 8493725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 15/200 14/2000 Szymanski-PT-a08-CTLFireability-2024-01 3418436 m, 252208 m/sec, 12730107 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 20/200 19/2000 Szymanski-PT-a08-CTLFireability-2024-01 4615003 m, 239313 m/sec, 16823126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 25/200 24/2000 Szymanski-PT-a08-CTLFireability-2024-01 5779419 m, 232883 m/sec, 20828962 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 30/200 29/2000 Szymanski-PT-a08-CTLFireability-2024-01 6958231 m, 235762 m/sec, 24803588 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 35/200 34/2000 Szymanski-PT-a08-CTLFireability-2024-01 8086295 m, 225612 m/sec, 28453513 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 40/200 40/2000 Szymanski-PT-a08-CTLFireability-2024-01 9610421 m, 304825 m/sec, 32648713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 45/200 43/2000 Szymanski-PT-a08-CTLFireability-2024-01 10326507 m, 143217 m/sec, 37257108 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 50/200 49/2000 Szymanski-PT-a08-CTLFireability-2024-01 11621688 m, 259036 m/sec, 41360395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 55/200 54/2000 Szymanski-PT-a08-CTLFireability-2024-01 12868186 m, 249299 m/sec, 45379361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 60/200 59/2000 Szymanski-PT-a08-CTLFireability-2024-01 14070994 m, 240561 m/sec, 49283205 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 65/200 63/2000 Szymanski-PT-a08-CTLFireability-2024-01 15190241 m, 223849 m/sec, 52958699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 70/200 68/2000 Szymanski-PT-a08-CTLFireability-2024-01 16319183 m, 225788 m/sec, 56675361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 75/200 73/2000 Szymanski-PT-a08-CTLFireability-2024-01 17445818 m, 225327 m/sec, 60397265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 80/200 77/2000 Szymanski-PT-a08-CTLFireability-2024-01 18581424 m, 227121 m/sec, 64178033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 85/200 82/2000 Szymanski-PT-a08-CTLFireability-2024-01 19718591 m, 227433 m/sec, 67994247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 90/200 87/2000 Szymanski-PT-a08-CTLFireability-2024-01 20862303 m, 228742 m/sec, 71824876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 95/200 91/2000 Szymanski-PT-a08-CTLFireability-2024-01 22003016 m, 228142 m/sec, 75679647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 100/200 96/2000 Szymanski-PT-a08-CTLFireability-2024-01 23143928 m, 228182 m/sec, 79549931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 105/200 100/2000 Szymanski-PT-a08-CTLFireability-2024-01 24275057 m, 226225 m/sec, 83387836 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 110/200 105/2000 Szymanski-PT-a08-CTLFireability-2024-01 25399179 m, 224824 m/sec, 87213652 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 115/200 110/2000 Szymanski-PT-a08-CTLFireability-2024-01 26524424 m, 225049 m/sec, 91054318 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 120/200 114/2000 Szymanski-PT-a08-CTLFireability-2024-01 27650538 m, 225222 m/sec, 94868309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 125/200 119/2000 Szymanski-PT-a08-CTLFireability-2024-01 28751681 m, 220228 m/sec, 98628049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 130/200 123/2000 Szymanski-PT-a08-CTLFireability-2024-01 29858583 m, 221380 m/sec, 102390133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 135/200 128/2000 Szymanski-PT-a08-CTLFireability-2024-01 30963224 m, 220928 m/sec, 106144311 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 140/200 132/2000 Szymanski-PT-a08-CTLFireability-2024-01 32054883 m, 218331 m/sec, 109883850 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 145/200 137/2000 Szymanski-PT-a08-CTLFireability-2024-01 33150200 m, 219063 m/sec, 113611113 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 150/200 141/2000 Szymanski-PT-a08-CTLFireability-2024-01 34217777 m, 213515 m/sec, 117264818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 155/200 146/2000 Szymanski-PT-a08-CTLFireability-2024-01 35321183 m, 220681 m/sec, 121016618 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 160/200 150/2000 Szymanski-PT-a08-CTLFireability-2024-01 36408962 m, 217555 m/sec, 124736278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 165/200 155/2000 Szymanski-PT-a08-CTLFireability-2024-01 37507848 m, 219777 m/sec, 128464134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 170/200 159/2000 Szymanski-PT-a08-CTLFireability-2024-01 38606349 m, 219700 m/sec, 132179523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 175/200 163/2000 Szymanski-PT-a08-CTLFireability-2024-01 39692231 m, 217176 m/sec, 135865127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 180/200 168/2000 Szymanski-PT-a08-CTLFireability-2024-01 40764292 m, 214412 m/sec, 139515084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 185/200 172/2000 Szymanski-PT-a08-CTLFireability-2024-01 41862644 m, 219670 m/sec, 143222382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 190/200 177/2000 Szymanski-PT-a08-CTLFireability-2024-01 42953311 m, 218133 m/sec, 146914717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 195/200 181/2000 Szymanski-PT-a08-CTLFireability-2024-01 44040154 m, 217368 m/sec, 150598984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 200/200 186/2000 Szymanski-PT-a08-CTLFireability-2024-01 45128276 m, 217624 m/sec, 154281334 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 4 (type EXCL) for Szymanski-PT-a08-CTLFireability-2024-01 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 76 (type EXCL) for 57 Szymanski-PT-a08-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 Szymanski-PT-a08-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 3395 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 76 (type EXCL) for Szymanski-PT-a08-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/199 5/5 Szymanski-PT-a08-CTLFireability-2024-01 1128661 m, -8799923 m/sec, 4465349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 4 (type EXCL) for Szymanski-PT-a08-CTLFireability-2024-01 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-15: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 57 Szymanski-PT-a08-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for Szymanski-PT-a08-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 20
[[35mlola[0m][I] fired transitions : 22
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 Szymanski-PT-a08-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for Szymanski-PT-a08-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 47 Szymanski-PT-a08-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 241 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for Szymanski-PT-a08-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 96
[[35mlola[0m][I] fired transitions : 120
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 Szymanski-PT-a08-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 260 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for Szymanski-PT-a08-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 37 Szymanski-PT-a08-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 282 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for Szymanski-PT-a08-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 Szymanski-PT-a08-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 307 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 5/307 3/2000 Szymanski-PT-a08-CTLFireability-2024-09 631381 m, 126276 m/sec, 3922930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 10/307 5/2000 Szymanski-PT-a08-CTLFireability-2024-09 1184024 m, 110528 m/sec, 7992380 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 15/307 8/2000 Szymanski-PT-a08-CTLFireability-2024-09 1915156 m, 146226 m/sec, 11885251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 20/307 11/2000 Szymanski-PT-a08-CTLFireability-2024-09 2597982 m, 136565 m/sec, 15626863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 25/307 14/2000 Szymanski-PT-a08-CTLFireability-2024-09 3206491 m, 121701 m/sec, 19276511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 30/307 16/2000 Szymanski-PT-a08-CTLFireability-2024-09 3771747 m, 113051 m/sec, 22868336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 35/307 18/2000 Szymanski-PT-a08-CTLFireability-2024-09 4309310 m, 107512 m/sec, 26394942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 40/307 20/2000 Szymanski-PT-a08-CTLFireability-2024-09 4824992 m, 103136 m/sec, 29905382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 45/307 22/2000 Szymanski-PT-a08-CTLFireability-2024-09 5324598 m, 99921 m/sec, 33370794 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 50/307 24/2000 Szymanski-PT-a08-CTLFireability-2024-09 5818456 m, 98771 m/sec, 36827438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 55/307 26/2000 Szymanski-PT-a08-CTLFireability-2024-09 6301803 m, 96669 m/sec, 40233788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 60/307 28/2000 Szymanski-PT-a08-CTLFireability-2024-09 6764126 m, 92464 m/sec, 43610703 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 281
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 65/307 30/2000 Szymanski-PT-a08-CTLFireability-2024-09 7231392 m, 93453 m/sec, 46992238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 288
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 70/307 32/2000 Szymanski-PT-a08-CTLFireability-2024-09 7707965 m, 95314 m/sec, 50368244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 294
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 75/307 34/2000 Szymanski-PT-a08-CTLFireability-2024-09 8224243 m, 103255 m/sec, 53783344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 301
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 80/307 36/2000 Szymanski-PT-a08-CTLFireability-2024-09 8758780 m, 106907 m/sec, 57182468 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 85/307 39/2000 Szymanski-PT-a08-CTLFireability-2024-09 9327249 m, 113693 m/sec, 60640213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 90/307 41/2000 Szymanski-PT-a08-CTLFireability-2024-09 9940268 m, 122603 m/sec, 64137882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 95/307 44/2000 Szymanski-PT-a08-CTLFireability-2024-09 10568135 m, 125573 m/sec, 67690109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 329
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 100/307 49/2000 Szymanski-PT-a08-CTLFireability-2024-09 11666443 m, 219661 m/sec, 71616138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 339
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 105/307 51/2000 Szymanski-PT-a08-CTLFireability-2024-09 12121802 m, 91071 m/sec, 75992024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 345
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 110/307 53/2000 Szymanski-PT-a08-CTLFireability-2024-09 12744592 m, 124558 m/sec, 79502429 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 352
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 115/307 56/2000 Szymanski-PT-a08-CTLFireability-2024-09 13357856 m, 122652 m/sec, 82984578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 360
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 120/307 58/2000 Szymanski-PT-a08-CTLFireability-2024-09 13945487 m, 117526 m/sec, 86427758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 366
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 125/307 61/2000 Szymanski-PT-a08-CTLFireability-2024-09 14545440 m, 119990 m/sec, 89877526 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 130/307 63/2000 Szymanski-PT-a08-CTLFireability-2024-09 15127812 m, 116474 m/sec, 93322981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 380
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 135/307 65/2000 Szymanski-PT-a08-CTLFireability-2024-09 15690203 m, 112478 m/sec, 96752441 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSzymanski-PT-a08-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSzymanski-PT-a08-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-06: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-10: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2024-11: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Szymanski-PT-a08-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 141/307 68/2000 Szymanski-PT-a08-CTLFireability-2024-09 16213692 m, 104697 m/sec, 99932672 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 394
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Szymanski-PT-a08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Szymanski-PT-a08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r401-tall-171690535300834"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Szymanski-PT-a08.tgz
mv Szymanski-PT-a08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;