MCC'2024- Execution of r401-tall-171690534300396

About the Execution of LoLA for StigmergyElection-PT-11a

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
4254.728	142204.00	183082.00	602.20	FFFFFFFTFTFFTFFF	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r401-tall-171690534300396.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..........................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is StigmergyElection-PT-11a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r401-tall-171690534300396
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 154M
-rw-r--r-- 1 mcc users 8.6K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 99K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:00 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 23 08:00 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 08:00 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 08:00 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.5K Apr 11 21:02 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 59K Apr 11 21:02 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.2K Apr 11 20:30 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 24K Apr 11 20:30 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 08:00 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 08:00 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 153M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-00
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-01
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-02
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-03
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-04
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-05
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-06
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-07
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-08
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-09
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-10
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-11
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-12
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-13
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-14
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717126231115

FORMULA StigmergyElection-PT-11a-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
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[[35mlola[0m] [1m[31mStigmergyElection-PT-11a-LTLFireability-00: LTL false LTL model checker[0m
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[[35mlola[0m] [1m[32mStigmergyElection-PT-11a-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-11a-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-11a-LTLFireability-11: LTL false LTL model checker[0m
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[[35mlola[0m] [1m[31mStigmergyElection-PT-11a-LTLFireability-13: LTL false LTL model checker[0m
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[[35mlola[0m]
[[35mlola[0m] Time elapsed: 142 secs. Pages in use: 2

BK_STOP 1717126373319

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-09: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-09: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-10: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-09: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-10: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-09: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-10: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][I] LAUNCH task # 15 (type CNST) for 12 StigmergyElection-PT-11a-LTLFireability-04
[[35mlola[0m][I] time limit : 0 sec
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[[35mlola[0m][I] LAUNCH task # 31 (type CNST) for 28 StigmergyElection-PT-11a-LTLFireability-08
[[35mlola[0m][I] time limit : 0 sec
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[[35mlola[0m][I] FINISHED task # 15 (type CNST) for StigmergyElection-PT-11a-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 31 (type CNST) for StigmergyElection-PT-11a-LTLFireability-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
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[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-09: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for StigmergyElection-PT-11a-LTLFireability-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 236228
[[35mlola[0m][I] fired transitions : 1692822
[[35mlola[0m][I] time used : 12
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 StigmergyElection-PT-11a-LTLFireability-14
[[35mlola[0m][I] time limit : 266 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 26
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 28 StigmergyElection-PT-11a-LTLFireability-08
[[35mlola[0m][I] time limit : 288 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 24
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 StigmergyElection-PT-11a-LTLFireability-07
[[35mlola[0m][I] time limit : 314 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 StigmergyElection-PT-11a-LTLFireability-05
[[35mlola[0m][I] time limit : 345 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 25
[[35mlola[0m][I] fired transitions : 25
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 StigmergyElection-PT-11a-LTLFireability-03
[[35mlola[0m][I] time limit : 384 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 40
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 StigmergyElection-PT-11a-LTLFireability-02
[[35mlola[0m][I] time limit : 432 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 27
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 StigmergyElection-PT-11a-LTLFireability-01
[[35mlola[0m][I] time limit : 494 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 24
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 35 StigmergyElection-PT-11a-LTLFireability-09
[[35mlola[0m][I] time limit : 576 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-11a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-11a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-11a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-11a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-11a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mStigmergyElection-PT-11a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-11a-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-11a-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-11a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-11a-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-09: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-11a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 63 EG EXCL 0/576 1/2000 StigmergyElection-PT-11a-LTLFireability-09 1989 m, 397 m/sec, 10772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2047
[[35mlola[0m][I] fired transitions : 11253
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 StigmergyElection-PT-11a-LTLFireability-11
[[35mlola[0m][I] time limit : 691 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 14
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 StigmergyElection-PT-11a-LTLFireability-06
[[35mlola[0m][I] time limit : 864 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 14
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 StigmergyElection-PT-11a-LTLFireability-00
[[35mlola[0m][I] time limit : 1153 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 13
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 StigmergyElection-PT-11a-LTLFireability-13
[[35mlola[0m][I] time limit : 1729 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 48 StigmergyElection-PT-11a-LTLFireability-12
[[35mlola[0m][I] time limit : 3459 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 49 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4095
[[35mlola[0m][I] fired transitions : 33781
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyElection-PT-11a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is StigmergyElection-PT-11a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r401-tall-171690534300396"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/StigmergyElection-PT-11a.tgz
mv StigmergyElection-PT-11a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;