About the Execution of LoLA for StigmergyElection-PT-10a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4585.268 | 589436.00 | 606399.00 | 1693.10 | FTFFFFTFFTTTFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r401-tall-171690534300378.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is StigmergyElection-PT-10a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r401-tall-171690534300378
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 51M
-rw-r--r-- 1 mcc users 7.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Apr 23 08:00 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 23 08:00 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 23 08:00 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 23 08:00 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 11 19:58 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 117K Apr 11 19:58 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Apr 11 19:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 47K Apr 11 19:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 08:00 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 08:00 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 50M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-00
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-01
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-02
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-03
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-04
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-05
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-06
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-07
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-08
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-09
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-10
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2024-11
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2023-12
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2023-13
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2023-14
FORMULA_NAME StigmergyElection-PT-10a-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717121910397
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2023-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-10a-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-10a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyElection-PT-10a-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-10a-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-10a-CTLFireability-2024-03: AGAF false state space /EFEG[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-10a-CTLFireability-2024-04: AGAF false state space /EFEG[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-10a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyElection-PT-10a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-10a-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-10a-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyElection-PT-10a-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyElection-PT-10a-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyElection-PT-10a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-10a-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyElection-PT-10a-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-10a-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyElection-PT-10a-CTLFireability-2023-15: CONJ false state space /EXEF[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 589 secs. Pages in use: 46
BK_STOP 1717122499833
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-03: AGAF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-04: AGAF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-15: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 22 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-03: AGAF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-04: AGAF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-15: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 27 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-03: AGAF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-04: AGAF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-15: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 32 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 StigmergyElection-PT-10a-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 162 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for StigmergyElection-PT-10a-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1033
[[35mlola[0m][I] fired transitions : 6188
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 StigmergyElection-PT-10a-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 169 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 45 StigmergyElection-PT-10a-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 56 (type EQUN) for 12 StigmergyElection-PT-10a-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 12 StigmergyElection-PT-10a-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for StigmergyElection-PT-10a-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN) for 9 StigmergyElection-PT-10a-CTLFireability-2024-03
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[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type EQUN) for StigmergyElection-PT-10a-CTLFireability-2024-04
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] FINISHED task # 62 (type EQUN) for StigmergyElection-PT-10a-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 67 (type EQUN) for StigmergyElection-PT-10a-CTLFireability-2024-03
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mStigmergyElection-PT-10a-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-03: AGAF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-04: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-10: CTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-12: CTL 0 1 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 2/178 1/2000 StigmergyElection-PT-10a-CTLFireability-2024-10 87904 m, 17580 m/sec, 1296487 t fired, .
[[35mlola[0m][.] 69 EF STEQ 1/3564 0/5 StigmergyElection-PT-10a-CTLFireability-2024-03 sara not yet started (preprocessing).
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[[35mlola[0m][I] FINISHED task # 69 (type EQUN) for StigmergyElection-PT-10a-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for StigmergyElection-PT-10a-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 119150
[[35mlola[0m][I] fired transitions : 1820163
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 45 StigmergyElection-PT-10a-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 209 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for StigmergyElection-PT-10a-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 21
[[35mlola[0m][I] fired transitions : 20
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 StigmergyElection-PT-10a-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 254 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mStigmergyElection-PT-10a-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mStigmergyElection-PT-10a-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-10a-CTLFireability-2023-15: CONJ false state space /EXEF[0m
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[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-03: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-04: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 37 CTL EXCL 5/274 3/2000 StigmergyElection-PT-10a-CTLFireability-2023-12 659125 m, 131825 m/sec, 2877080 t fired, .
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[[35mlola[0m][.] [1m[31mStigmergyElection-PT-10a-CTLFireability-2023-15: CONJ false state space /EXEF[0m
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[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-03: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-04: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 37 CTL EXCL 10/274 7/2000 StigmergyElection-PT-10a-CTLFireability-2023-12 1548496 m, 177874 m/sec, 6682970 t fired, .
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[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-03: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-04: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 37 CTL EXCL 15/274 9/2000 StigmergyElection-PT-10a-CTLFireability-2023-12 2001547 m, 90610 m/sec, 10218371 t fired, .
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[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-04: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-10a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 37 CTL EXCL 35/274 20/2000 StigmergyElection-PT-10a-CTLFireability-2023-12 4629848 m, 69581 m/sec, 27600196 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 40/274 21/2000 StigmergyElection-PT-10a-CTLFireability-2023-12 4754508 m, 24932 m/sec, 29078464 t fired, .
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[[35mlola[0m][.] 22 CTL EXCL 3/391 1/2000 StigmergyElection-PT-10a-CTLFireability-2024-07 151400 m, 30280 m/sec, 1654167 t fired, .
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[[35mlola[0m][.] 22 CTL EXCL 8/391 2/2000 StigmergyElection-PT-10a-CTLFireability-2024-07 420105 m, 53741 m/sec, 4967500 t fired, .
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[[35mlola[0m][.] 22 CTL EXCL 13/391 3/2000 StigmergyElection-PT-10a-CTLFireability-2024-07 675864 m, 51151 m/sec, 8669269 t fired, .
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[[35mlola[0m][.] 16 CTL EXCL 139/453 43/2000 StigmergyElection-PT-10a-CTLFireability-2024-05 10157440 m, 66045 m/sec, 131744884 t fired, .
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[[35mlola[0m][.] 53 EFEG EXCL 0/1506 1/2000 StigmergyElection-PT-10a-CTLFireability-2024-04 335 m, 67 m/sec, 1320 t fired, .
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[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyElection-PT-10a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is StigmergyElection-PT-10a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r401-tall-171690534300378"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/StigmergyElection-PT-10a.tgz
mv StigmergyElection-PT-10a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;