MCC'2024- Execution of r401-tall-171690534200338

About the Execution of LoLA for StigmergyElection-PT-07b

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
0.000	2561215.00	0.00	0.00	T??????F?F??????	normal

Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r401-tall-171690534200338.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is StigmergyElection-PT-07b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r401-tall-171690534200338
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.8M
-rw-r--r-- 1 mcc users 6.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 59K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Apr 23 08:00 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 08:00 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 19 07:34 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 19 19:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 10K Apr 11 18:42 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 105K Apr 11 18:42 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.0K Apr 11 18:41 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Apr 11 18:41 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 08:00 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 08:00 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 3.4M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-00
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-01
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-02
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-03
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-04
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-05
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-06
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-07
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-08
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-09
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-10
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2024-11
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2023-12
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2023-13
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2023-14
FORMULA_NAME StigmergyElection-PT-07b-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717114816262

FORMULA StigmergyElection-PT-07b-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07b-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07b-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717117377477

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-00: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-07: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-10: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-15: DISJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
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[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-00: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-07: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-10: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-15: DISJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][I] LAUNCH task # 30 (type CNST) for 29 StigmergyElection-PT-07b-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 0 sec
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[[35mlola[0m][I] FINISHED task # 30 (type CNST) for StigmergyElection-PT-07b-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-07b-CTLFireability-2024-07: INITIAL false preprocessing[0m
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[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-00: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-10: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-15: DISJ 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-00: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-10: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-15: DISJ 0 0 0 0 2 0 0 0
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[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 StigmergyElection-PT-07b-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 198 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for StigmergyElection-PT-07b-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 54
[[35mlola[0m][I] fired transitions : 163
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 StigmergyElection-PT-07b-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 210 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-07b-CTLFireability-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mStigmergyElection-PT-07b-CTLFireability-2024-09: CTL false CTL model checker[0m
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[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-00: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-10: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-15: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 CTL EXCL 1/210 1/2000 StigmergyElection-PT-07b-CTLFireability-2024-11 20947 m, 4189 m/sec, 70298 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-10: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2023-15: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 CTL EXCL 6/210 1/2000 StigmergyElection-PT-07b-CTLFireability-2024-11 132916 m, 22393 m/sec, 532968 t fired, .
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[[35mlola[0m][.] StigmergyElection-PT-07b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 42 CTL EXCL 31/210 7/2000 StigmergyElection-PT-07b-CTLFireability-2024-11 1660675 m, 113608 m/sec, 8200306 t fired, .
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[[35mlola[0m][.] 42 CTL EXCL 36/238 9/2000 StigmergyElection-PT-07b-CTLFireability-2024-11 2121396 m, 92144 m/sec, 10996371 t fired, .
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[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for StigmergyElection-PT-07b-CTLFireability-2024-04
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[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 StigmergyElection-PT-07b-CTLFireability-2023-14
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[[35mlola[0m][.] 51 CTL EXCL 15/331 3/2000 StigmergyElection-PT-07b-CTLFireability-2023-14 479760 m, 31671 m/sec, 3254887 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyElection-PT-07b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is StigmergyElection-PT-07b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r401-tall-171690534200338"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/StigmergyElection-PT-07b.tgz
mv StigmergyElection-PT-07b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;