About the Execution of LoLA for StigmergyCommit-PT-07a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
4676.048 | 767754.00 | 782092.00 | 1701.00 | FTFFTTFTFTFTFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r401-tall-171690533800170.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is StigmergyCommit-PT-07a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r401-tall-171690533800170
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.8M
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 60K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:59 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:59 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 23 07:59 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 23 07:59 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 11 17:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 107K Apr 11 17:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Apr 11 17:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 57K Apr 11 17:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:59 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:59 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 5.4M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-00
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-01
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-02
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-03
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-04
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-05
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-06
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-07
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-08
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-09
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-10
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2024-11
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2023-12
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2023-13
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2023-14
FORMULA_NAME StigmergyCommit-PT-07a-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717094064218
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2023-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyCommit-PT-07a-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mStigmergyCommit-PT-07a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyCommit-PT-07a-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyCommit-PT-07a-CTLFireability-2024-02: DISJ false DISJ[0m
[[35mlola[0m] [1m[31mStigmergyCommit-PT-07a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyCommit-PT-07a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyCommit-PT-07a-CTLFireability-2024-05: EF true findpath[0m
[[35mlola[0m] [1m[31mStigmergyCommit-PT-07a-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF true tscc_search[0m
[[35mlola[0m] [1m[31mStigmergyCommit-PT-07a-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyCommit-PT-07a-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyCommit-PT-07a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mStigmergyCommit-PT-07a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyCommit-PT-07a-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyCommit-PT-07a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyCommit-PT-07a-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mStigmergyCommit-PT-07a-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 767 secs. Pages in use: 32
BK_STOP 1717094831972
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 StigmergyCommit-PT-07a-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for StigmergyCommit-PT-07a-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 52
[[35mlola[0m][I] fired transitions : 104
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 StigmergyCommit-PT-07a-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 53 (type FNDP) for 6 StigmergyCommit-PT-07a-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 6 StigmergyCommit-PT-07a-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type FNDP) for StigmergyCommit-PT-07a-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 54 (type EQUN) for StigmergyCommit-PT-07a-CTLFireability-2024-02 (obsolete)
[[35mlola[0m][I] FINISHED task # 54 (type EQUN) for StigmergyCommit-PT-07a-CTLFireability-2024-02
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 59 (type EQUN) for 25 StigmergyCommit-PT-07a-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for 25 StigmergyCommit-PT-07a-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 59 (type EQUN) for StigmergyCommit-PT-07a-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 61 (type EQUN) for StigmergyCommit-PT-07a-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 62 (type FNDP) for 19 StigmergyCommit-PT-07a-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 19 StigmergyCommit-PT-07a-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type FNDP) for StigmergyCommit-PT-07a-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 63 (type EQUN) for StigmergyCommit-PT-07a-CTLFireability-2024-05 (obsolete)
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for StigmergyCommit-PT-07a-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mStigmergyCommit-PT-07a-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mStigmergyCommit-PT-07a-CTLFireability-2024-05: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-02: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 4/257 2/2000 StigmergyCommit-PT-07a-CTLFireability-2024-08 320565 m, 64113 m/sec, 3148452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mStigmergyCommit-PT-07a-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mStigmergyCommit-PT-07a-CTLFireability-2024-05: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-02: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 9/257 3/2000 StigmergyCommit-PT-07a-CTLFireability-2024-08 701168 m, 76120 m/sec, 7235934 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 14/257 5/2000 StigmergyCommit-PT-07a-CTLFireability-2024-08 1079117 m, 75589 m/sec, 11347618 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 94/257 30/2000 StigmergyCommit-PT-07a-CTLFireability-2024-08 6849820 m, 71072 m/sec, 74441953 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-02: DISJ 0 1 0 0 4 0 0 1
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 99/257 31/2000 StigmergyCommit-PT-07a-CTLFireability-2024-08 7195772 m, 69190 m/sec, 78286069 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 50 CTL EXCL 2/268 1/2000 StigmergyCommit-PT-07a-CTLFireability-2023-15 143969 m, 28793 m/sec, 943921 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-02: DISJ 0 1 0 0 4 0 0 1
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 47 CTL EXCL 15/282 9/2000 StigmergyCommit-PT-07a-CTLFireability-2023-14 2033711 m, 131302 m/sec, 11518708 t fired, .
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[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 StigmergyCommit-PT-07a-CTLFireability-2024-11
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-02: DISJ 0 1 0 0 4 0 0 1
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 38 CTL EXCL 4/307 1/2000 StigmergyCommit-PT-07a-CTLFireability-2024-11 115294 m, 23058 m/sec, 1835211 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 9/307 2/2000 StigmergyCommit-PT-07a-CTLFireability-2024-11 299082 m, 36757 m/sec, 4976494 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 38 CTL EXCL 14/307 2/2000 StigmergyCommit-PT-07a-CTLFireability-2024-11 455211 m, 31225 m/sec, 7671005 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 38 CTL EXCL 39/307 6/2000 StigmergyCommit-PT-07a-CTLFireability-2024-11 1235545 m, 32275 m/sec, 22323978 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 84/307 12/2000 StigmergyCommit-PT-07a-CTLFireability-2024-11 2737827 m, 31665 m/sec, 50497902 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 38 CTL EXCL 124/307 18/2000 StigmergyCommit-PT-07a-CTLFireability-2024-11 4060663 m, 33603 m/sec, 75381928 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-02: DISJ 0 1 0 0 4 0 0 1
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 38 CTL EXCL 209/307 30/2000 StigmergyCommit-PT-07a-CTLFireability-2024-11 6899060 m, 33473 m/sec, 129281456 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-02: DISJ 0 1 0 0 4 0 0 1
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 38 CTL EXCL 214/307 31/2000 StigmergyCommit-PT-07a-CTLFireability-2024-11 7063590 m, 32906 m/sec, 132434071 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-02: DISJ 0 1 0 0 4 0 0 1
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 38 CTL EXCL 219/307 31/2000 StigmergyCommit-PT-07a-CTLFireability-2024-11 7232617 m, 33805 m/sec, 135700744 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 38 CTL EXCL 224/307 32/2000 StigmergyCommit-PT-07a-CTLFireability-2024-11 7399924 m, 33461 m/sec, 138940539 t fired, .
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[[35mlola[0m][I] result : false
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[[35mlola[0m][.] 32 CTL EXCL 5/350 1/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 208183 m, 41636 m/sec, 3061220 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 10/350 2/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 429927 m, 44348 m/sec, 6402328 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 15/350 3/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 617666 m, 37547 m/sec, 9408658 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 32 CTL EXCL 20/350 4/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 826283 m, 41723 m/sec, 12686474 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 25/350 5/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 1052383 m, 45220 m/sec, 16320032 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 30/350 6/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 1269242 m, 43371 m/sec, 19730954 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 35/350 7/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 1489404 m, 44032 m/sec, 23268826 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 40/350 8/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 1715261 m, 45171 m/sec, 26825449 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 45/350 9/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 1939541 m, 44856 m/sec, 30357256 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 50/350 10/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 2150855 m, 42262 m/sec, 33750969 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 65/350 13/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 2812612 m, 43566 m/sec, 44247284 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 70/350 13/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 3032360 m, 43949 m/sec, 47707278 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 80/350 15/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 3467825 m, 43313 m/sec, 54654019 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 150/350 28/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 6455457 m, 44071 m/sec, 102367953 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 155/350 29/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 6672626 m, 43433 m/sec, 105848404 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 160/350 30/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 6888169 m, 43108 m/sec, 109308394 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 165/350 31/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 7098287 m, 42023 m/sec, 112694175 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 170/350 32/2000 StigmergyCommit-PT-07a-CTLFireability-2024-09 7314841 m, 43310 m/sec, 116186763 t fired, .
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[[35mlola[0m][.] StigmergyCommit-PT-07a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 9 CTL EXCL 13/497 3/2000 StigmergyCommit-PT-07a-CTLFireability-2024-02 655096 m, 43749 m/sec, 8215700 t fired, .
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[[35mlola[0m][.] 9 CTL EXCL 23/497 5/2000 StigmergyCommit-PT-07a-CTLFireability-2024-02 1161794 m, 52437 m/sec, 15148222 t fired, .
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[[35mlola[0m][.] 9 CTL EXCL 53/497 12/2000 StigmergyCommit-PT-07a-CTLFireability-2024-02 2676130 m, 49998 m/sec, 35941143 t fired, .
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[[35mlola[0m][.] 9 CTL EXCL 58/497 13/2000 StigmergyCommit-PT-07a-CTLFireability-2024-02 2925569 m, 49887 m/sec, 39456808 t fired, .
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[[35mlola[0m][.] 9 CTL EXCL 63/497 14/2000 StigmergyCommit-PT-07a-CTLFireability-2024-02 3181552 m, 51196 m/sec, 42938302 t fired, .
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[[35mlola[0m][.] 9 CTL EXCL 68/497 15/2000 StigmergyCommit-PT-07a-CTLFireability-2024-02 3436275 m, 50944 m/sec, 46501561 t fired, .
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[[35mlola[0m][.] 9 CTL EXCL 73/497 16/2000 StigmergyCommit-PT-07a-CTLFireability-2024-02 3679592 m, 48663 m/sec, 49825778 t fired, .
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[[35mlola[0m][.] 9 CTL EXCL 78/497 17/2000 StigmergyCommit-PT-07a-CTLFireability-2024-02 3918229 m, 47727 m/sec, 53189381 t fired, .
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[[35mlola[0m][.] 9 CTL EXCL 138/497 30/2000 StigmergyCommit-PT-07a-CTLFireability-2024-02 6915832 m, 49508 m/sec, 95027141 t fired, .
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyCommit-PT-07a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is StigmergyCommit-PT-07a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r401-tall-171690533800170"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/StigmergyCommit-PT-07a.tgz
mv StigmergyCommit-PT-07a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;