fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r399-tall-171690530500530
Last Updated
July 7, 2024

About the Execution of GreatSPN+red for Sudoku-COL-AN16

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
12308.632 3600000.00 13294535.00 1710.20 T?????????FT???? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r399-tall-171690530500530.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool greatspnxred
Input is Sudoku-COL-AN16, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r399-tall-171690530500530
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 7.5K Apr 12 12:21 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Apr 12 12:21 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Apr 12 10:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Apr 12 10:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Apr 23 08:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 23 08:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 08:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 08:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 12 14:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 131K Apr 12 14:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Apr 12 12:33 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 64K Apr 12 12:33 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 08:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 08:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 5 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 6.5K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-00
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-01
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-02
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-03
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-04
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-05
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-06
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-07
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-08
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-09
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-10
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-11
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-12
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-13
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-14
FORMULA_NAME Sudoku-COL-AN16-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717049007064

Invoking MCC driver with
BK_TOOL=greatspnxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Sudoku-COL-AN16
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool greatspn
Invoking reducer
Running Version 202405141337
[2024-05-30 06:03:28] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-05-30 06:03:28] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-30 06:03:28] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2024-05-30 06:03:28] [WARNING] Using fallBack plugin, rng conformance not checked
[2024-05-30 06:03:28] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 525 ms
[2024-05-30 06:03:28] [INFO ] Imported 4 HL places and 1 HL transitions for a total of 4864 PT places and 4096.0 transition bindings in 13 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 17 ms.
[2024-05-30 06:03:29] [INFO ] Built PT skeleton of HLPN with 4 places and 1 transitions 4 arcs in 4 ms.
[2024-05-30 06:03:29] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Computed a total of 4 stabilizing places and 1 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 4 transition count 1
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 12 formulas.
FORMULA Sudoku-COL-AN16-CTLFireability-2024-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Sudoku-COL-AN16-CTLFireability-2024-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Sudoku-COL-AN16-CTLFireability-2024-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
All 16 properties of the HLPN use transition enablings in a way that makes the skeleton too coarse.
Domain [N(16), N(16)] of place Rows breaks symmetries in sort N
[2024-05-30 06:03:29] [INFO ] Unfolded HLPN to a Petri net with 4864 places and 4096 transitions 16384 arcs in 137 ms.
[2024-05-30 06:03:29] [INFO ] Unfolded 13 HLPN properties in 33 ms.
Support contains 768 out of 4864 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 4864/4864 places, 4096/4096 transitions.
Reduce places removed 4096 places and 0 transitions.
Iterating post reduction 0 with 4096 rules applied. Total rules applied 4096 place count 768 transition count 4096
Applied a total of 4096 rules in 80 ms. Remains 768 /4864 variables (removed 4096) and now considering 4096/4096 (removed 0) transitions.
// Phase 1: matrix 4096 rows 768 cols
[2024-05-30 06:04:46] [INFO ] Computed 47 invariants in 393 ms
[2024-05-30 06:04:46] [INFO ] Implicit Places using invariants in 668 ms returned []
[2024-05-30 06:04:46] [INFO ] Invariant cache hit.
[2024-05-30 06:05:02] [INFO ] Implicit Places using invariants and state equation in 15853 ms returned []
Implicit Place search using SMT with State Equation took 16551 ms to find 0 implicit places.
Running 0 sub problems to find dead transitions.
Search for dead transitions found 0 dead transitions in 2ms
Starting structural reductions in LTL mode, iteration 1 : 768/4864 places, 4096/4096 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16670 ms. Remains : 768/4864 places, 4096/4096 transitions.
Support contains 768 out of 768 places after structural reductions.
[2024-05-30 06:05:07] [INFO ] Flatten gal took : 2065 ms
[2024-05-30 06:05:30] [INFO ] Flatten gal took : 2825 ms
[2024-05-30 06:05:54] [INFO ] Input system was already deterministic with 4096 transitions.
Reduction of identical properties reduced properties to check from 10 to 1
RANDOM walk for 896 steps (0 resets) in 932 ms. (0 steps per ms) remains 0/1 properties
[2024-05-30 06:06:24] [INFO ] Flatten gal took : 1512 ms
[2024-05-30 06:06:45] [INFO ] Flatten gal took : 2472 ms
[2024-05-30 06:07:06] [INFO ] Input system was already deterministic with 4096 transitions.
Computed a total of 768 stabilizing places and 4096 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 768 transition count 4096
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 8 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:07:32] [INFO ] Flatten gal took : 155 ms
[2024-05-30 06:07:32] [INFO ] Flatten gal took : 272 ms
[2024-05-30 06:07:33] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 8 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:07:35] [INFO ] Flatten gal took : 304 ms
[2024-05-30 06:07:36] [INFO ] Flatten gal took : 436 ms
[2024-05-30 06:07:37] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:07:37] [INFO ] Flatten gal took : 154 ms
[2024-05-30 06:07:38] [INFO ] Flatten gal took : 198 ms
[2024-05-30 06:07:38] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 6 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:07:39] [INFO ] Flatten gal took : 357 ms
[2024-05-30 06:07:40] [INFO ] Flatten gal took : 515 ms
[2024-05-30 06:07:41] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 30 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:07:41] [INFO ] Flatten gal took : 167 ms
[2024-05-30 06:07:41] [INFO ] Flatten gal took : 208 ms
[2024-05-30 06:07:42] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 7 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:07:42] [INFO ] Flatten gal took : 230 ms
[2024-05-30 06:07:43] [INFO ] Flatten gal took : 330 ms
[2024-05-30 06:07:43] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 6 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:07:45] [INFO ] Flatten gal took : 161 ms
[2024-05-30 06:07:45] [INFO ] Flatten gal took : 201 ms
[2024-05-30 06:07:45] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 6 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:07:46] [INFO ] Flatten gal took : 177 ms
[2024-05-30 06:07:46] [INFO ] Flatten gal took : 232 ms
[2024-05-30 06:07:47] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:07:54] [INFO ] Flatten gal took : 358 ms
[2024-05-30 06:07:55] [INFO ] Flatten gal took : 523 ms
[2024-05-30 06:07:56] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 22 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:08:00] [INFO ] Flatten gal took : 258 ms
[2024-05-30 06:08:01] [INFO ] Flatten gal took : 363 ms
[2024-05-30 06:08:02] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 18 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:08:06] [INFO ] Flatten gal took : 247 ms
[2024-05-30 06:08:07] [INFO ] Flatten gal took : 330 ms
[2024-05-30 06:08:07] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 18 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:08:08] [INFO ] Flatten gal took : 250 ms
[2024-05-30 06:08:08] [INFO ] Flatten gal took : 343 ms
[2024-05-30 06:08:09] [INFO ] Input system was already deterministic with 4096 transitions.
Starting structural reductions in LTL mode, iteration 0 : 768/768 places, 4096/4096 transitions.
Applied a total of 0 rules in 5 ms. Remains 768 /768 variables (removed 0) and now considering 4096/4096 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 768/768 places, 4096/4096 transitions.
[2024-05-30 06:08:11] [INFO ] Flatten gal took : 279 ms
[2024-05-30 06:08:11] [INFO ] Flatten gal took : 400 ms
[2024-05-30 06:08:12] [INFO ] Input system was already deterministic with 4096 transitions.
[2024-05-30 06:08:16] [INFO ] Flatten gal took : 2738 ms
[2024-05-30 06:08:38] [INFO ] Flatten gal took : 2591 ms
[2024-05-30 06:08:59] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 696 ms.
[2024-05-30 06:08:59] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 768 places, 4096 transitions and 12288 arcs took 17 ms.
Total runtime 330841 ms.
There are residual formulas that ITS could not solve within timeout
----------------------------------------------------------------------
GreatSPN-meddly tool, MCC 2023
----------------------------------------------------------------------

Running Sudoku-COL-AN16

IS_COLORED=
IS_NUPN=

LOADING PETRI NET FILE /home/mcc/execution/411/model.pnml (PNML) ...
PNML VERSION 2009, P/T NET.
COLOR CLASSES: 0
CONSTANTS: 0
PLACES: 768
TRANSITIONS: 4096
COLOR VARS: 0
MEASURES: 0
LOADING TIME: [User 0.067s, Sys 0.007s]


SAVING FILE /home/mcc/execution/411/model (.net / .def) ...
EXPORT TIME: [User 0.008s, Sys 0.004s]


----------------------------------------------------------------------
GreatSPN/Meddly.
Copyright (C) 1987-2022, University of Torino, Italy.
website: https://github.com/greatspn/SOURCES

Based on MEDDLY version 0.16.0
Copyright (C) 2009, Iowa State University Research Foundation, Inc.
website: http://meddly.sourceforge.net

Process ID: 562
MODEL NAME: /home/mcc/execution/411/model
768 places, 4096 transitions.

Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Sudoku-COL-AN16"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="greatspnxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool greatspnxred"
echo " Input is Sudoku-COL-AN16, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r399-tall-171690530500530"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Sudoku-COL-AN16.tgz
mv Sudoku-COL-AN16 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;