Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r398-tall-171690527700164.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool greatspn
Input is StigmergyCommit-PT-06b, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r398-tall-171690527700164
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.2M
-rw-r--r-- 1 mcc users 7.6K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 35K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K May 19 07:17 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K May 19 16:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 19 07:34 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 19:22 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Apr 11 17:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 191K Apr 11 17:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Apr 11 17:55 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 57K Apr 11 17:55 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:59 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:59 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 3.7M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-00
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-01
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-02
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-03
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-04
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-05
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-06
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-07
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-08
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-09
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-10
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-11
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-12
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-13
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-14
FORMULA_NAME StigmergyCommit-PT-06b-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717004135055

Invoking MCC driver with
BK_TOOL=greatspn
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=StigmergyCommit-PT-06b
BK_MEMORY_CONFINEMENT=16384
Not applying reductions.
Model is PT
LTLFireability PT
----------------------------------------------------------------------
GreatSPN-meddly tool, MCC 2023
----------------------------------------------------------------------

Running StigmergyCommit-PT-06b

IS_COLORED=
IS_NUPN=1

LOADING model.pnml ...
MODEL CLASS: P/T NET WITH NUPN EXTENSION
PLACES: 2140
TRANSITIONS: 6760
CONSTANTS: 0
TEMPLATE VARS: 0
ARCS: 67803
NUPN UNITS: 15
LOADING TIME: 3.397

SAVING AS /home/mcc/execution/model.(net/def) ...
exportGspn useExt=true
SAVING TIME: 0.251
SAVING NAME MAP FILE /home/mcc/execution/model.id2name ...
SAVING NUPN UNITS AS FILE /home/mcc/execution/model.nu ...
TOTAL TIME: 4.443
OK.
----------------------------------------------------------------------
GreatSPN/Meddly.
Copyright (C) 1987-2022, University of Torino, Italy.
website: https://github.com/greatspn/SOURCES

Based on MEDDLY version 0.16.0
Copyright (C) 2009, Iowa State University Research Foundation, Inc.
website: http://meddly.sourceforge.net

Process ID: 482
MODEL NAME: /home/mcc/execution/model
2140 places, 6760 transitions.

Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Building monolithic NSF...
FORMULA StigmergyCommit-PT-06b-LTLFireability-03 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA StigmergyCommit-PT-06b-LTLFireability-06 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA StigmergyCommit-PT-06b-LTLFireability-11 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA StigmergyCommit-PT-06b-LTLFireability-14 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA StigmergyCommit-PT-06b-LTLFireability-13 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA StigmergyCommit-PT-06b-LTLFireability-04 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA StigmergyCommit-PT-06b-LTLFireability-08 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA StigmergyCommit-PT-06b-LTLFireability-10 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA StigmergyCommit-PT-06b-LTLFireability-00 CANNOT_COMPUTE
FORMULA StigmergyCommit-PT-06b-LTLFireability-01 CANNOT_COMPUTE
FORMULA StigmergyCommit-PT-06b-LTLFireability-02 CANNOT_COMPUTE
FORMULA StigmergyCommit-PT-06b-LTLFireability-05 CANNOT_COMPUTE
FORMULA StigmergyCommit-PT-06b-LTLFireability-07 CANNOT_COMPUTE
FORMULA StigmergyCommit-PT-06b-LTLFireability-09 CANNOT_COMPUTE
FORMULA StigmergyCommit-PT-06b-LTLFireability-12 CANNOT_COMPUTE
FORMULA StigmergyCommit-PT-06b-LTLFireability-15 CANNOT_COMPUTE
Ok.
EXITCODE: 0
----------------------------------------------------------------------

BK_STOP 1717005643546

--------------------
content from stderr:

MEDDLY ERROR: Insufficient memory

MEDDLY ERROR: Insufficient memory

MEDDLY ERROR: Insufficient memory

MEDDLY ERROR: Insufficient memory

MEDDLY ERROR: Insufficient memory

MEDDLY ERROR: Insufficient memory

MEDDLY ERROR: Insufficient memory

MEDDLY ERROR: Insufficient memory

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyCommit-PT-06b"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="greatspn"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool greatspn"
echo " Input is StigmergyCommit-PT-06b, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r398-tall-171690527700164"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/StigmergyCommit-PT-06b.tgz
mv StigmergyCommit-PT-06b execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;