Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r395-smll-171683824200209.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool gold2023
Input is SmallOperatingSystem-PT-MT8192DC4096, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r395-smll-171683824200209
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.5K Apr 23 07:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Apr 23 07:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 12 14:13 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K Apr 12 14:13 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Apr 12 14:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Apr 12 14:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Apr 23 07:57 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Apr 23 07:57 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 13 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 8.1K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-00
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-01
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-03
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-04
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-05
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-06
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-07
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-08
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-09
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-10
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-13
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-14
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-15

=== Now, execution of the tool begins

BK_START 1716974371828

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=gold2023
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT8192DC4096
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2024-05-29 09:19:34] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2024-05-29 09:19:34] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-29 09:19:34] [INFO ] Load time of PNML (sax parser for PT used): 115 ms
[2024-05-29 09:19:34] [INFO ] Transformed 9 places.
[2024-05-29 09:19:34] [INFO ] Transformed 8 transitions.
[2024-05-29 09:19:34] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 229 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 27 ms.
Working with output stream class java.io.PrintStream
Incomplete random walk after 12293 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=409 ) properties (out of 16) seen :5
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-15 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-14 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-06 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-04 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 323 ms. (steps per millisecond=30 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 197 ms. (steps per millisecond=50 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 242 ms. (steps per millisecond=41 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 124 ms. (steps per millisecond=80 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 129 ms. (steps per millisecond=77 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 72 ms. (steps per millisecond=138 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 100 ms. (steps per millisecond=100 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 87 ms. (steps per millisecond=114 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 130 ms. (steps per millisecond=76 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 144 ms. (steps per millisecond=69 ) properties (out of 11) seen :0
Running SMT prover for 11 properties.
// Phase 1: matrix 8 rows 9 cols
[2024-05-29 09:19:36] [INFO ] Computed 4 invariants in 3 ms
[2024-05-29 09:19:36] [INFO ] [Real]Absence check using 4 positive place invariants in 4 ms returned sat
[2024-05-29 09:19:37] [INFO ] After 318ms SMT Verify possible using all constraints in real domain returned unsat :5 sat :0 real:6
[2024-05-29 09:19:37] [INFO ] [Nat]Absence check using 4 positive place invariants in 3 ms returned sat
[2024-05-29 09:19:37] [INFO ] After 43ms SMT Verify possible using state equation in natural domain returned unsat :7 sat :4
[2024-05-29 09:19:37] [INFO ] After 83ms SMT Verify possible using trap constraints in natural domain returned unsat :7 sat :4
Attempting to minimize the solution found.
Minimization took 38 ms.
[2024-05-29 09:19:37] [INFO ] After 231ms SMT Verify possible using all constraints in natural domain returned unsat :7 sat :4
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-13 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-10 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-09 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-07 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-01 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 11 Parikh solutions to 4 different solutions.
TestFail conflict detected : techniques TOPOLOGICAL PARIKH_WALK answered differently (true)on formula SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-01
TestFail conflict detected : techniques TOPOLOGICAL PARIKH_WALK answered differently (true)on formula SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-03 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Finished Parikh walk after 17976 steps, including 0 resets, run visited all 1 properties in 30 ms. (steps per millisecond=599 )
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-05 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 2 properties in 1800 ms.
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 21 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 21 ms. Remains : 9/9 places, 8/8 transitions.
Incomplete random walk after 12293 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=1756 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 504860 steps, run timeout after 3001 ms. (steps per millisecond=168 ) properties seen :{}
Probabilistic random walk after 504860 steps, saw 276961 distinct states, run finished after 3002 ms. (steps per millisecond=168 ) properties seen :0
Running SMT prover for 2 properties.
[2024-05-29 09:19:42] [INFO ] Invariant cache hit.
[2024-05-29 09:19:42] [INFO ] After 27ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2024-05-29 09:19:42] [INFO ] [Nat]Absence check using 4 positive place invariants in 1 ms returned sat
[2024-05-29 09:19:42] [INFO ] After 17ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2024-05-29 09:19:42] [INFO ] After 30ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 11 ms.
[2024-05-29 09:19:42] [INFO ] After 73ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-08 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Finished Parikh walk after 17978 steps, including 0 resets, run visited all 1 properties in 44 ms. (steps per millisecond=408 )
FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 2 properties in 307 ms.
All properties solved without resorting to model-checking.
Total runtime 7981 ms.
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT8192DC4096
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1716974384783

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 61 (type EXCL) for 0 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-00
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 52 (type FNDP) for 6 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type EQUN) for 6 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type SRCH) for 6 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 61 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-00
lola: result : true
lola: markings : 1258
lola: fired transitions : 1257
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 56 (type EXCL) for 6 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-53.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 53 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02
lola: result : false
lola: CANCELED task # 52 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02 (obsolete)
lola: CANCELED task # 55 (type SRCH) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02 (obsolete)
lola: CANCELED task # 56 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02 (obsolete)
lola: LAUNCH task # 84 (type EXCL) for 33 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 49 (type FNDP) for 3 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type EQUN) for 3 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 65 (type FNDP) for 12 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 52 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02
lola: result : unknown
lola: fired transitions : 82576
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 65 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-04
lola: result : true
lola: fired transitions : 1153
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 68 (type FNDP) for 9 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-50.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 68 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-03
lola: result : true
lola: fired transitions : 284538
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: LAUNCH task # 104 (type FNDP) for 36 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages

lola: FINISHED task # 50 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-01
lola: result : false
lola: CANCELED task # 49 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-01 (obsolete)
lola: LAUNCH task # 130 (type FNDP) for 21 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 131 (type EQUN) for 21 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 49 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-01
lola: result : unknown
lola: fired transitions : 393685
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-131.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 131 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-07
lola: result : false
lola: CANCELED task # 130 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-07 (obsolete)
lola: LAUNCH task # 127 (type FNDP) for 39 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 128 (type EQUN) for 39 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 130 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-07
lola: result : unknown
lola: fired transitions : 12968
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-128.sara.

lola: FINISHED task # 128 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-13
lola: result : false
lola: CANCELED task # 127 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-13 (obsolete)
lola: LAUNCH task # 112 (type FNDP) for 27 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 113 (type EQUN) for 27 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 127 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-13
lola: result : unknown
lola: fired transitions : 10311
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-113.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 113 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-09
lola: result : false
lola: CANCELED task # 112 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-09 (obsolete)
lola: LAUNCH task # 87 (type FNDP) for 15 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type EQUN) for 15 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 112 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-09
lola: result : unknown
lola: fired transitions : 6430
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-88.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 87 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-05
lola: result : true
lola: fired transitions : 6053
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 88 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-05 (obsolete)
lola: LAUNCH task # 147 (type FNDP) for 24 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 148 (type EQUN) for 24 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 88 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-05
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-148.sara.
lola: FINISHED task # 147 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-08
lola: result : true
lola: fired transitions : 6296
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 148 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-08 (obsolete)
lola: LAUNCH task # 139 (type FNDP) for 42 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 140 (type EQUN) for 42 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 148 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-08
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-140.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 139 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-14
lola: result : true
lola: fired transitions : 2802
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 140 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-14 (obsolete)
lola: LAUNCH task # 94 (type FNDP) for 18 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 95 (type EQUN) for 18 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 140 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-14
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 94 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-06
lola: result : true
lola: fired transitions : 670
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 95 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-06 (obsolete)
lola: LAUNCH task # 103 (type FNDP) for 30 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 105 (type EQUN) for 30 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 95 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-06
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-105.sara.

lola: FINISHED task # 105 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-10
lola: result : false
lola: CANCELED task # 103 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-10 (obsolete)
lola: LAUNCH task # 118 (type FNDP) for 45 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 119 (type EQUN) for 45 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 103 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-10
lola: result : unknown
lola: fired transitions : 7242
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-119.sara.
lola: FINISHED task # 118 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-15
lola: result : true
lola: fired transitions : 3384
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 119 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-15 (obsolete)
lola: LAUNCH task # 107 (type EQUN) for 36 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 109 (type SRCH) for 36 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 119 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-15
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-107.sara.
lola: FINISHED task # 109 (type SRCH) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12
lola: result : true
lola: markings : 86453
lola: fired transitions : 144022
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 104 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12 (obsolete)
lola: CANCELED task # 107 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12 (obsolete)
lola: LAUNCH task # 80 (type FNDP) for 33 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type EQUN) for 33 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SRCH) for 33 SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 104 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12
lola: result : unknown
lola: fired transitions : 291769
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 107 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-81.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 81 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11
lola: result : false
lola: CANCELED task # 80 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11 (obsolete)
lola: CANCELED task # 83 (type SRCH) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11 (obsolete)
lola: CANCELED task # 84 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-00: EF true tandem / relaxed
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-01: EF false state equation
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-02: EF false state equation
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-03: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-04: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-05: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-06: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-07: EF false state equation
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-08: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-09: AG true state equation
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-10: AG true state equation
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-11: EF false state equation
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-12: AG false tandem / insertion
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-13: EF false state equation
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-14: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-ReachabilityCardinality-2024-15: EF true findpath


Time elapsed: 1 secs. Pages in use: 3

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT8192DC4096"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="gold2023"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool gold2023"
echo " Input is SmallOperatingSystem-PT-MT8192DC4096, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r395-smll-171683824200209"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT8192DC4096.tgz
mv SmallOperatingSystem-PT-MT8192DC4096 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;