MCC'2024- Execution of r379-smll-171683812300332

About the Execution of LoLA for SmallOperatingSystem-PT-MT8192DC4096

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
6083.159	77973.00	79155.00	365.60	FFFFFFFFFTFFTFFT	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r379-smll-171683812300332.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is SmallOperatingSystem-PT-MT8192DC4096, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r379-smll-171683812300332
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.5K Apr 23 07:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Apr 23 07:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 12 14:13 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K Apr 12 14:13 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Apr 12 14:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Apr 12 14:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Apr 23 07:57 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Apr 23 07:57 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 13 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 8.1K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717136483131

FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU false state space /ER[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m] [1m[32mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 77 secs. Pages in use: 225

BK_STOP 1717136561104

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 3 (type CNST) for 0 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 3 (type CNST) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 10 (type CNST) for 7 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 10 (type CNST) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01
[[35mlola[0m][I] result : false
[*** LOG ERROR #0001 ***] [2024-05-31 06:21:23] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06
[[35mlola[0m][I] time limit : 144 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 69 (type FNDP) for 24 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 24 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 70 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04 (obsolete)
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 73 (type FNDP) for 53 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 53 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 80 (type EQUN) for 31 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 74 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11 (obsolete)
[[35mlola[0m][I] LAUNCH task # 82 (type FNDP) for 46 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 83 (type EQUN) for 46 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 82 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 83 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10 (obsolete)
[[35mlola[0m][I] FINISHED task # 80 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 83 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 5/327 17/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 2371702 m, 474340 m/sec, 4722156 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 10/327 34/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 4906974 m, 507054 m/sec, 9791876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 15/327 51/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 7371142 m, 492833 m/sec, 14719407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 20/327 68/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 9835257 m, 492823 m/sec, 19646838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 25/327 85/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 12307776 m, 494503 m/sec, 24591070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 30/327 101/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 14584302 m, 455305 m/sec, 29143382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 35/327 118/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 17070696 m, 497278 m/sec, 34103138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 40/327 130/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 19027863 m, 391433 m/sec, 38017312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 45/327 143/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 20958845 m, 386196 m/sec, 41879119 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 50/327 155/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 22877297 m, 383690 m/sec, 45715868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 55/327 168/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 24767327 m, 378006 m/sec, 49495773 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 60/327 180/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 26680463 m, 382627 m/sec, 53321888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 65/327 192/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 28614758 m, 386859 m/sec, 57190323 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 70/327 205/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 30557448 m, 388538 m/sec, 61075547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-04: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC4096-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 LTL EXCL 75/327 218/2000 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06 32570845 m, 402679 m/sec, 65102177 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 33625440
[[35mlola[0m][I] fired transitions : 67174416
[[35mlola[0m][I] time used : 77
[[35mlola[0m][I] memory pages used : 225
[[35mlola[0m][I] LAUNCH task # 66 (type EXCL) for 65 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15
[[35mlola[0m][I] time limit : 352 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 66 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 62 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14
[[35mlola[0m][I] time limit : 391 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 16393
[[35mlola[0m][I] fired transitions : 16396
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 59 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13
[[35mlola[0m][I] time limit : 440 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 16386
[[35mlola[0m][I] fired transitions : 16386
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 56 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12
[[35mlola[0m][I] time limit : 503 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 8193
[[35mlola[0m][I] fired transitions : 8192
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09
[[35mlola[0m][I] time limit : 587 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08
[[35mlola[0m][I] time limit : 704 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 16386
[[35mlola[0m][I] fired transitions : 16386
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07
[[35mlola[0m][I] time limit : 880 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 16386
[[35mlola[0m][I] fired transitions : 16386
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03
[[35mlola[0m][I] time limit : 1174 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4104
[[35mlola[0m][I] fired transitions : 4104
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 77 (type EXCL) for 31 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05
[[35mlola[0m][I] time limit : 1761 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 77 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4096
[[35mlola[0m][I] fired transitions : 4095
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02
[[35mlola[0m][I] time limit : 3523 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 16387
[[35mlola[0m][I] fired transitions : 16388
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT8192DC4096"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is SmallOperatingSystem-PT-MT8192DC4096, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r379-smll-171683812300332"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT8192DC4096.tgz
mv SmallOperatingSystem-PT-MT8192DC4096 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;