About the Execution of LoLA for SmallOperatingSystem-PT-MT8192DC2048
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16206.340 | 348088.00 | 352955.00 | 1317.80 | ???????????????T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r379-smll-171683812300322.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is SmallOperatingSystem-PT-MT8192DC2048, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r379-smll-171683812300322
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 496K
-rw-r--r-- 1 mcc users 7.7K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Apr 23 07:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Apr 23 07:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Apr 23 07:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 12 14:02 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Apr 12 14:02 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 14:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Apr 12 14:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Apr 23 07:57 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Apr 23 07:57 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 13 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 8.1K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717135521647
FORMULA SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717135869735
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 51 (type EQUN) for 33 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 51 (type EQUN) for SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 52 (type FNDP) for 45 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 53 (type EQUN) for 45 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type FNDP) for SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 53 (type EQUN) for SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15 (obsolete)
[[35mlola[0m][I] FINISHED task # 53 (type EQUN) for SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 5/240 6/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 1195784 m, 239156 m/sec, 4720308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 10/240 11/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 2376255 m, 236094 m/sec, 9442868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 15/240 16/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 3527031 m, 230155 m/sec, 14046632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 20/240 21/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 4649390 m, 224471 m/sec, 18536698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 25/240 26/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 5777410 m, 225604 m/sec, 23049422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 30/240 30/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 6824345 m, 209387 m/sec, 27237757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 35/240 35/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 7970496 m, 229230 m/sec, 31823024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 40/240 40/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 9110007 m, 227902 m/sec, 36381710 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 45/240 45/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 10242252 m, 226449 m/sec, 40911344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 50/240 50/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 11340697 m, 219689 m/sec, 45305746 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 55/240 55/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 12436290 m, 219118 m/sec, 49688737 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 60/240 60/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 13538922 m, 220526 m/sec, 54099897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 65/240 65/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 14630705 m, 218356 m/sec, 58467652 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 70/240 69/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 15723612 m, 218581 m/sec, 62839898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 75/240 74/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 16822692 m, 219816 m/sec, 67236855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 80/240 79/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 17927586 m, 220978 m/sec, 71657060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 85/240 84/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 19046173 m, 223717 m/sec, 76132043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 90/240 89/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 20192644 m, 229294 m/sec, 80718580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 95/240 94/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 21278318 m, 217134 m/sec, 85061887 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 100/240 99/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 22373272 m, 218990 m/sec, 89442340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 105/240 104/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 23503449 m, 226035 m/sec, 93963691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 110/240 109/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 24668530 m, 233016 m/sec, 98624670 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 115/240 113/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 25722635 m, 210821 m/sec, 102824873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 120/240 116/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 26608425 m, 177158 m/sec, 106367745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 125/240 120/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 27522308 m, 182776 m/sec, 110022974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 130/240 123/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 28451515 m, 185841 m/sec, 113739501 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 135/240 127/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 29342505 m, 178198 m/sec, 117303173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 140/240 130/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 30218509 m, 175200 m/sec, 120806902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 145/240 133/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 31071936 m, 170685 m/sec, 124220329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 150/240 136/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 31875625 m, 160737 m/sec, 127434825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 155/240 140/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 32709079 m, 166690 m/sec, 130768370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 160/240 143/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 33597003 m, 177584 m/sec, 134319779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 165/240 147/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 34519647 m, 184528 m/sec, 138010053 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 170/240 150/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 35417596 m, 179589 m/sec, 141601553 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 175/240 153/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 36286051 m, 173691 m/sec, 145075094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 180/240 157/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 37230269 m, 188843 m/sec, 148851655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 185/240 161/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 38165570 m, 187060 m/sec, 152718406 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 190/240 165/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 39125212 m, 191928 m/sec, 157037451 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 195/240 169/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 40069643 m, 188886 m/sec, 161288046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 200/240 173/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 41025317 m, 191134 m/sec, 165589245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 205/240 177/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 41978931 m, 190722 m/sec, 169881168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 210/240 181/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 42953953 m, 195004 m/sec, 174269441 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 215/240 185/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 43935888 m, 196387 m/sec, 178688828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 220/240 189/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 44877765 m, 188375 m/sec, 182927926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 225/240 193/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 45834795 m, 191406 m/sec, 187235226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 230/240 197/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 46790587 m, 191158 m/sec, 191536956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 235/240 201/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 47741877 m, 190258 m/sec, 195818425 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 240/240 205/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 48698954 m, 191415 m/sec, 200125936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 1 (type EXCL) for SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 3355 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 16386
[[35mlola[0m][I] fired transitions : 30723
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 1 (type EXCL) for SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 279 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 18433
[[35mlola[0m][I] fired transitions : 67593
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 304 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 5/304 12/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 2856354 m, 571270 m/sec, 5696783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 10/304 25/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 5728616 m, 574452 m/sec, 11441777 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 15/304 37/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 8597905 m, 573857 m/sec, 17180820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 20/304 48/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 11425585 m, 565536 m/sec, 22836641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 25/304 58/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 13759602 m, 466803 m/sec, 27490716 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 30/304 66/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 15654145 m, 378908 m/sec, 31280109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 35/304 74/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 17546951 m, 378561 m/sec, 35066031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 40/304 82/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 19430985 m, 376806 m/sec, 38834404 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 291
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 45/304 90/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 21319715 m, 377746 m/sec, 42612171 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 299
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 50/304 98/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 23247142 m, 385485 m/sec, 46467340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 55/304 106/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 25226743 m, 395920 m/sec, 50412526 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 60/304 119/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 28170031 m, 588657 m/sec, 56299582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 328
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 65/304 131/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 30992033 m, 564400 m/sec, 61944045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 70/304 142/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 33811132 m, 563819 m/sec, 67582703 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 75/304 154/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 36614213 m, 560616 m/sec, 73189318 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 363
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 80/304 164/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 38890723 m, 455302 m/sec, 77728370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 373
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 85/304 171/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 40711127 m, 364080 m/sec, 81369478 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 380
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 90/304 179/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 42531263 m, 364027 m/sec, 85010043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 388
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mSmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2023-15: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 95/304 185/2000 SmallOperatingSystem-PT-MT8192DC2048-CTLFireability-2024-10 43949113 m, 283570 m/sec, 87845974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 394
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT8192DC2048"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is SmallOperatingSystem-PT-MT8192DC2048, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r379-smll-171683812300322"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT8192DC2048.tgz
mv SmallOperatingSystem-PT-MT8192DC2048 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;