About the Execution of LoLA for SimpleLoadBal-PT-20
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.203 | 1392122.00 | 1473871.00 | 4847.40 | ???????F???????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r379-smll-171683812000178.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is SimpleLoadBal-PT-20, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r379-smll-171683812000178
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.5M
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 93K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Apr 23 07:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K May 19 07:33 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 19 19:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 13 12:01 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 94K Apr 13 12:01 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 13 12:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Apr 13 12:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 19 07:16 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K May 19 15:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 2.0M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-00
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-01
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-02
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-03
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-04
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-05
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-06
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-07
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-08
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-09
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-10
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2024-11
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2023-12
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2023-13
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2023-14
FORMULA_NAME SimpleLoadBal-PT-20-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717118925891
FORMULA SimpleLoadBal-PT-20-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717120318013
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 SimpleLoadBal-PT-20-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 52 (type EQUN) for 21 SimpleLoadBal-PT-20-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type EQUN) for SimpleLoadBal-PT-20-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 49 (type FNDP) for 0 SimpleLoadBal-PT-20-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 53 (type EQUN) for 0 SimpleLoadBal-PT-20-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type EQUN) for SimpleLoadBal-PT-20-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][W] CANCELED task # 49 (type FNDP) for SimpleLoadBal-PT-20-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][I] FINISHED task # 49 (type FNDP) for SimpleLoadBal-PT-20-CTLFireability-2024-00
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 2
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 2/256 1/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 24308 m, 4861 m/sec, 74940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 7 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 7/256 1/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 163307 m, 27799 m/sec, 599420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 12 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 12/256 2/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 301852 m, 27709 m/sec, 1116770 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 17 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 17/256 3/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 434515 m, 26532 m/sec, 1609301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 22 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 22/256 3/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 574945 m, 28086 m/sec, 2142152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 27 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 27/256 4/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 706880 m, 26387 m/sec, 2614745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 32 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 32/256 4/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 841834 m, 26990 m/sec, 3115299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 37 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 37/256 5/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 983448 m, 28322 m/sec, 3634622 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 42 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 42/256 6/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 1124099 m, 28130 m/sec, 4134536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 47 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 47/256 6/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 1263651 m, 27910 m/sec, 4665088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 52 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 52/256 7/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 1403599 m, 27989 m/sec, 5109288 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 57 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 57/256 8/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 1542517 m, 27783 m/sec, 5596901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 62 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 62/256 8/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 1682487 m, 27994 m/sec, 6057994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 67 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 67/256 9/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 1821096 m, 27721 m/sec, 6536468 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 72 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 72/256 9/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 1960530 m, 27886 m/sec, 6977461 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 77 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 77/256 10/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 2092656 m, 26425 m/sec, 7421508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 82 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 82/256 11/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 2232606 m, 27990 m/sec, 7876091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 87 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 87/256 11/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 2370287 m, 27536 m/sec, 8398358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 92 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 92/256 12/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 2509103 m, 27763 m/sec, 8835673 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 97 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 97/256 13/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 2648414 m, 27862 m/sec, 9286876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 102 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 102/256 13/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 2789328 m, 28182 m/sec, 9670496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 107 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 107/256 14/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 2927503 m, 27635 m/sec, 10152890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 112 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 112/256 14/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 3065032 m, 27505 m/sec, 10676011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 117 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 117/256 15/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 3203739 m, 27741 m/sec, 11135902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 122 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 122/256 16/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 3342413 m, 27734 m/sec, 11644170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 127 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 127/256 16/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 3482519 m, 28021 m/sec, 12141664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 132 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 132/256 17/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 3623075 m, 28111 m/sec, 12523692 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 137 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 137/256 17/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 3762275 m, 27840 m/sec, 13007109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 142 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 142/256 18/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 3902129 m, 27970 m/sec, 13488022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 147 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 147/256 19/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 4041742 m, 27922 m/sec, 13886563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 152 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 152/256 19/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 4180709 m, 27793 m/sec, 14366531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 157 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 157/256 20/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 4318652 m, 27588 m/sec, 14825300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 162 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 162/256 21/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 4457499 m, 27769 m/sec, 15276215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 167 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 167/256 21/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 4595288 m, 27557 m/sec, 15736577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 172 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 172/256 22/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 4732923 m, 27527 m/sec, 16141869 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 177 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 177/256 22/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 4871068 m, 27629 m/sec, 16540930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 182 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 182/256 23/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 5010642 m, 27914 m/sec, 16915990 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 187 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 187/256 24/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 5149206 m, 27712 m/sec, 17246139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 192 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 192/256 24/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 5287213 m, 27601 m/sec, 17584815 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 197 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 197/256 25/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 5428747 m, 28306 m/sec, 18040313 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 202 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 202/256 25/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 5569256 m, 28101 m/sec, 18380140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 207 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 207/256 26/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 5708368 m, 27822 m/sec, 18679911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 212 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 212/256 27/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 5846394 m, 27605 m/sec, 19083185 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 217 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 217/256 27/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 5984618 m, 27644 m/sec, 19522048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 222 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 222/256 28/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 6122499 m, 27576 m/sec, 19922643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 227 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 227/256 29/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 6265814 m, 28663 m/sec, 20341620 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 232 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 232/256 29/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 6403262 m, 27489 m/sec, 20719446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 237 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 237/256 30/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 6540906 m, 27528 m/sec, 21113919 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 242 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 242/256 30/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 6679170 m, 27652 m/sec, 21490375 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 247 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 247/256 31/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 6822256 m, 28617 m/sec, 21893649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 252 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 252/256 32/2000 SimpleLoadBal-PT-20-CTLFireability-2024-01 6960412 m, 27631 m/sec, 22267539 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 257 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 4 (type EXCL) for SimpleLoadBal-PT-20-CTLFireability-2024-01 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 262 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 SimpleLoadBal-PT-20-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 SimpleLoadBal-PT-20-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 3338 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for SimpleLoadBal-PT-20-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3328
[[35mlola[0m][I] fired transitions : 4918
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/256 1/5 SimpleLoadBal-PT-20-CTLFireability-2024-01 143076 m, -1363467 m/sec, 517234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 267 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/256 2/5 SimpleLoadBal-PT-20-CTLFireability-2024-01 285269 m, 28438 m/sec, 1059468 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 272 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 15/256 2/5 SimpleLoadBal-PT-20-CTLFireability-2024-01 425613 m, 28068 m/sec, 1576789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 277 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 20/256 3/5 SimpleLoadBal-PT-20-CTLFireability-2024-01 568446 m, 28566 m/sec, 2114281 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 282 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 25/256 4/5 SimpleLoadBal-PT-20-CTLFireability-2024-01 711340 m, 28578 m/sec, 2636104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 287 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 30/256 4/5 SimpleLoadBal-PT-20-CTLFireability-2024-01 851142 m, 27960 m/sec, 3137163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 292 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 35/256 5/5 SimpleLoadBal-PT-20-CTLFireability-2024-01 988266 m, 27424 m/sec, 3655143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 297 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 4 (type EXCL) for SimpleLoadBal-PT-20-CTLFireability-2024-01 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 SimpleLoadBal-PT-20-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 274 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 5/274 1/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 132920 m, 26584 m/sec, 612650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 307 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 10/274 2/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 261826 m, 25781 m/sec, 1223839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 312 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 15/274 2/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 391192 m, 25873 m/sec, 1849419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 317 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 20/274 3/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 519442 m, 25650 m/sec, 2463048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 322 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 25/274 3/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 646652 m, 25442 m/sec, 3062654 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 327 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 30/274 4/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 775736 m, 25816 m/sec, 3652874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 332 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 35/274 5/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 904773 m, 25807 m/sec, 4251899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 337 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 40/274 5/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 1033707 m, 25786 m/sec, 4852949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 342 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 45/274 6/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 1161969 m, 25652 m/sec, 5442490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 347 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 50/274 6/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 1289825 m, 25571 m/sec, 6029314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 352 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 55/274 7/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 1417724 m, 25579 m/sec, 6571495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 357 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 60/274 8/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 1544804 m, 25416 m/sec, 7147947 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 362 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 65/274 8/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 1672895 m, 25618 m/sec, 7703932 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 367 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 70/274 9/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 1799295 m, 25280 m/sec, 8252396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 372 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 75/274 9/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 1925721 m, 25285 m/sec, 8774126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 377 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 80/274 10/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 2051772 m, 25210 m/sec, 9364025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 382 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 85/274 10/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 2177599 m, 25165 m/sec, 9851487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 387 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 90/274 11/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 2304874 m, 25455 m/sec, 10451939 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 392 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 95/274 12/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 2430669 m, 25159 m/sec, 11014589 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 397 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 100/274 12/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 2556869 m, 25240 m/sec, 11513856 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 402 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 105/274 13/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 2683336 m, 25293 m/sec, 12095607 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 407 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 110/274 13/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 2809001 m, 25133 m/sec, 12565895 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 412 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 115/274 14/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 2934925 m, 25184 m/sec, 13117117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 417 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 120/274 14/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 3060854 m, 25185 m/sec, 13717235 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 422 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 125/274 15/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 3186329 m, 25095 m/sec, 14253637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 427 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 130/274 15/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 3312396 m, 25213 m/sec, 14831901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 432 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 135/274 16/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 3439257 m, 25372 m/sec, 15409302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 437 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 140/274 17/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 3564526 m, 25053 m/sec, 15877194 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 442 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 145/274 17/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 3690455 m, 25185 m/sec, 16451406 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 447 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 150/274 18/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 3816455 m, 25200 m/sec, 16977434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 452 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 155/274 18/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 3942733 m, 25255 m/sec, 17520722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 457 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 160/274 19/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 4069082 m, 25269 m/sec, 18054741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 462 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 165/274 19/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 4194771 m, 25137 m/sec, 18592658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 467 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 170/274 20/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 4319450 m, 24935 m/sec, 19148967 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 472 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 175/274 21/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 4444440 m, 24998 m/sec, 19668757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 477 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 180/274 21/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 4569869 m, 25085 m/sec, 20201525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 482 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 185/274 22/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 4694777 m, 24981 m/sec, 20756877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 487 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 190/274 22/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 4819690 m, 24982 m/sec, 21230768 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 492 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 195/274 23/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 4944765 m, 25015 m/sec, 21721712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 497 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 200/274 23/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 5068610 m, 24769 m/sec, 22106402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 502 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 205/274 24/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 5192373 m, 24752 m/sec, 22591077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 507 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 210/274 24/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 5315289 m, 24583 m/sec, 22958680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 512 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 215/274 25/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 5441281 m, 25198 m/sec, 23537365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 517 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 220/274 25/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 5564905 m, 24724 m/sec, 23936499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 522 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 225/274 26/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 5687271 m, 24473 m/sec, 24313217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 527 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 230/274 27/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 5811742 m, 24894 m/sec, 24816823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 532 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 235/274 27/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 5936833 m, 25018 m/sec, 25350935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 537 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 240/274 28/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 6061939 m, 25021 m/sec, 25816472 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 542 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 245/274 28/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 6187407 m, 25093 m/sec, 26360221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 547 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 250/274 29/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 6311823 m, 24883 m/sec, 26801421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 552 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 255/274 29/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 6434504 m, 24536 m/sec, 27224500 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 557 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 260/274 30/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 6559130 m, 24925 m/sec, 27740834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 562 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 265/274 30/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 6683339 m, 24841 m/sec, 28186506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 567 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 270/274 31/2000 SimpleLoadBal-PT-20-CTLFireability-2023-14 6808408 m, 25013 m/sec, 28667055 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 572 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 43 (type EXCL) for SimpleLoadBal-PT-20-CTLFireability-2023-14 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 SimpleLoadBal-PT-20-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 274 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 SimpleLoadBal-PT-20-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 3023 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 5/274 2/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 241482 m, 48296 m/sec, 1613841 t fired, .
[[35mlola[0m][.] 43 CTL EXCL 5/3023 1/5 SimpleLoadBal-PT-20-CTLFireability-2023-14 128491 m, -1335983 m/sec, 592937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 582 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 10/274 3/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 491934 m, 50090 m/sec, 3304396 t fired, .
[[35mlola[0m][.] 43 CTL EXCL 10/251 2/5 SimpleLoadBal-PT-20-CTLFireability-2023-14 260492 m, 26400 m/sec, 1216523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 587 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 15/274 4/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 743557 m, 50324 m/sec, 4980161 t fired, .
[[35mlola[0m][.] 43 CTL EXCL 15/251 2/5 SimpleLoadBal-PT-20-CTLFireability-2023-14 392878 m, 26477 m/sec, 1858449 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 592 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 20/274 5/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 994007 m, 50090 m/sec, 6658087 t fired, .
[[35mlola[0m][.] 43 CTL EXCL 20/251 3/5 SimpleLoadBal-PT-20-CTLFireability-2023-14 523921 m, 26208 m/sec, 2491756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 597 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 25/274 6/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 1243302 m, 49859 m/sec, 8311868 t fired, .
[[35mlola[0m][.] 43 CTL EXCL 25/251 4/5 SimpleLoadBal-PT-20-CTLFireability-2023-14 653488 m, 25913 m/sec, 3080109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 602 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 30/274 7/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 1493402 m, 50020 m/sec, 9915066 t fired, .
[[35mlola[0m][.] 43 CTL EXCL 30/251 4/5 SimpleLoadBal-PT-20-CTLFireability-2023-14 784213 m, 26145 m/sec, 3681260 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 607 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 35/274 9/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 1742945 m, 49908 m/sec, 11509439 t fired, .
[[35mlola[0m][.] 43 CTL EXCL 35/251 5/5 SimpleLoadBal-PT-20-CTLFireability-2023-14 910985 m, 25354 m/sec, 4272961 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 612 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 40/274 10/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 1989808 m, 49372 m/sec, 13054683 t fired, .
[[35mlola[0m][.] 43 CTL EXCL 40/251 5/5 SimpleLoadBal-PT-20-CTLFireability-2023-14 1037991 m, 25401 m/sec, 4873327 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 617 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 43 (type EXCL) for SimpleLoadBal-PT-20-CTLFireability-2023-14 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 45/274 11/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 2236296 m, 49297 m/sec, 14596780 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 622 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 50/274 12/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 2472176 m, 47176 m/sec, 16105534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 627 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 55/274 13/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 2718712 m, 49307 m/sec, 17640518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 632 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 60/274 14/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 2962582 m, 48774 m/sec, 19175352 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 637 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 65/274 15/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 3185990 m, 44681 m/sec, 20623511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 642 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 70/274 16/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 3417733 m, 46348 m/sec, 22153050 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 647 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 75/274 17/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 3656096 m, 47672 m/sec, 23602055 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 652 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 80/274 18/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 3891721 m, 47125 m/sec, 25134518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 657 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 85/274 19/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 4135331 m, 48722 m/sec, 26646758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 662 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 90/274 20/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 4373383 m, 47610 m/sec, 28147383 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 667 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 95/274 21/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 4611790 m, 47681 m/sec, 29626238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 672 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 100/274 22/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 4851847 m, 48011 m/sec, 31041048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 677 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 105/274 23/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 5103167 m, 50264 m/sec, 32411758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 682 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 110/274 25/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 5348046 m, 48975 m/sec, 33812151 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 687 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 115/274 26/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 5597832 m, 49957 m/sec, 35229679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 692 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 120/274 27/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 5846064 m, 49646 m/sec, 36620219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 697 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 125/274 28/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 6086535 m, 48094 m/sec, 38103226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 702 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 130/274 29/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 6327623 m, 48217 m/sec, 39541749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 707 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 135/274 30/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 6570231 m, 48521 m/sec, 40934669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 712 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 140/274 31/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 6822440 m, 50441 m/sec, 42361185 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 717 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 145/274 32/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 7075698 m, 50651 m/sec, 43741600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 722 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 150/274 33/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 7324869 m, 49834 m/sec, 45209799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 727 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 155/274 34/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 7576279 m, 50282 m/sec, 46516270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 732 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 160/274 35/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 7827108 m, 50165 m/sec, 47789918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 737 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 165/274 36/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 8070721 m, 48722 m/sec, 49180121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 742 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 170/274 37/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 8309767 m, 47809 m/sec, 50685997 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 747 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 175/274 39/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 8559791 m, 50004 m/sec, 51960868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 752 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 180/274 40/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 8807300 m, 49501 m/sec, 53326130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 757 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 185/274 41/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 9055847 m, 49709 m/sec, 54679850 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 762 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 190/274 42/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 9307537 m, 50338 m/sec, 56004874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 767 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 195/274 43/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 9554131 m, 49318 m/sec, 57396595 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 772 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 200/274 44/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 9802718 m, 49717 m/sec, 58696658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 777 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 205/274 45/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 10048991 m, 49254 m/sec, 60055072 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 782 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 210/274 46/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 10298548 m, 49911 m/sec, 61354005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 787 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 215/274 47/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 10541054 m, 48501 m/sec, 62817975 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 792 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 220/274 48/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 10780496 m, 47888 m/sec, 64139503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 797 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 225/274 49/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 11023813 m, 48663 m/sec, 65359868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 802 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 230/274 50/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 11268122 m, 48861 m/sec, 66702165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 807 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 235/274 51/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 11513315 m, 49038 m/sec, 67935765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 812 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 240/274 53/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 11759215 m, 49180 m/sec, 69405636 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 817 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 245/274 54/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 12006163 m, 49389 m/sec, 70771004 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 822 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 250/274 55/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 12247627 m, 48292 m/sec, 71993050 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 827 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 255/274 56/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 12493347 m, 49144 m/sec, 73387854 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 832 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 260/274 57/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 12735357 m, 48402 m/sec, 74695389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 837 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 265/274 58/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 12967990 m, 46526 m/sec, 75926880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 842 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 270/274 59/2000 SimpleLoadBal-PT-20-CTLFireability-2023-13 13206509 m, 47703 m/sec, 77252559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 847 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 40 (type EXCL) for SimpleLoadBal-PT-20-CTLFireability-2023-13 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 852 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 SimpleLoadBal-PT-20-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 274 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 SimpleLoadBal-PT-20-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 2748 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 5/274 2/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 355911 m, 71182 m/sec, 1324336 t fired, .
[[35mlola[0m][.] 40 CTL EXCL 5/2748 2/5 SimpleLoadBal-PT-20-CTLFireability-2023-13 227816 m, -2595738 m/sec, 1530507 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 857 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 10/274 4/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 713117 m, 71441 m/sec, 2645732 t fired, .
[[35mlola[0m][.] 40 CTL EXCL 10/249 3/5 SimpleLoadBal-PT-20-CTLFireability-2023-13 464287 m, 47294 m/sec, 3128588 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 862 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 15/274 5/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 1067490 m, 70874 m/sec, 3952508 t fired, .
[[35mlola[0m][.] 40 CTL EXCL 15/249 4/5 SimpleLoadBal-PT-20-CTLFireability-2023-13 700870 m, 47316 m/sec, 4691502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 867 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 20/274 7/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 1448475 m, 76197 m/sec, 5276002 t fired, .
[[35mlola[0m][.] 40 CTL EXCL 20/249 5/5 SimpleLoadBal-PT-20-CTLFireability-2023-13 945713 m, 48968 m/sec, 6333002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 872 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 40 (type EXCL) for SimpleLoadBal-PT-20-CTLFireability-2023-13 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 25/274 9/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 1820749 m, 74454 m/sec, 6535768 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 877 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 30/274 11/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 2205153 m, 76880 m/sec, 7781284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 882 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 35/274 12/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 2587516 m, 76472 m/sec, 9063438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 887 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 40/274 14/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 2969612 m, 76419 m/sec, 10312690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 892 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 45/274 16/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 3343919 m, 74861 m/sec, 11651913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 897 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 50/274 17/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 3713936 m, 74003 m/sec, 12826261 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 902 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 55/274 19/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 4080815 m, 73375 m/sec, 14033814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 907 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 60/274 21/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 4463052 m, 76447 m/sec, 15297289 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 912 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 65/274 22/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 4851085 m, 77606 m/sec, 16483806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 917 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 70/274 24/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 5255350 m, 80853 m/sec, 17521690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 922 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 75/274 26/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 5658298 m, 80589 m/sec, 18566378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 927 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 80/274 28/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 6046746 m, 77689 m/sec, 19694044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 932 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 85/274 29/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 6440880 m, 78826 m/sec, 20807426 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 937 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 90/274 31/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 6833894 m, 78602 m/sec, 21918731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 942 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 95/274 33/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 7235517 m, 80324 m/sec, 22961607 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 947 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 100/274 35/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 7641447 m, 81186 m/sec, 23921607 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 952 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 105/274 36/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 8038844 m, 79479 m/sec, 24900560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 957 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 110/274 38/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 8426047 m, 77440 m/sec, 26004664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 962 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 115/274 40/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 8826723 m, 80135 m/sec, 26948175 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 967 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 120/274 41/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 9226815 m, 80018 m/sec, 27903814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 972 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 125/274 43/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 9624863 m, 79609 m/sec, 28896062 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 977 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 130/274 45/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 10026441 m, 80315 m/sec, 29810408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 982 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 135/274 47/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 10416533 m, 78018 m/sec, 30893512 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 987 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 140/274 48/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 10780269 m, 72747 m/sec, 31798006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 992 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 145/274 50/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 11177098 m, 79365 m/sec, 32714222 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 997 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 150/274 52/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 11576241 m, 79828 m/sec, 33597967 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1002 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 155/274 53/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 11938222 m, 72396 m/sec, 34559174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1007 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 160/274 55/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 12337230 m, 79801 m/sec, 35445030 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1012 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 165/274 57/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 12726887 m, 77931 m/sec, 36457597 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1017 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 170/274 59/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 13120164 m, 78655 m/sec, 37353013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1022 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 175/274 60/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 13502901 m, 76547 m/sec, 38355699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1027 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 180/274 62/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 13892099 m, 77839 m/sec, 39314260 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1032 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 185/274 64/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 14287154 m, 79011 m/sec, 40170294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1037 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 190/274 65/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 14679838 m, 78536 m/sec, 41142853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1042 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 195/274 67/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 15050937 m, 74219 m/sec, 41985493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1047 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 200/274 69/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 15436454 m, 77103 m/sec, 43014250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1052 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 205/274 70/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 15828186 m, 78346 m/sec, 43866011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1057 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 210/274 72/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 16209935 m, 76349 m/sec, 44775811 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1062 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 215/274 74/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 16595527 m, 77118 m/sec, 45762056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1067 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 220/274 75/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 16986170 m, 78128 m/sec, 46727385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1072 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 225/274 77/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 17377325 m, 78231 m/sec, 47580346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1077 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 230/274 79/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 17763133 m, 77161 m/sec, 48449049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1082 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 235/274 80/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 18149319 m, 77237 m/sec, 49317061 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1087 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 240/274 82/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 18537551 m, 77646 m/sec, 50227424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1092 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 245/274 84/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 18923651 m, 77220 m/sec, 51090182 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1097 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 250/274 86/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 19307370 m, 76743 m/sec, 51969890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1102 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 255/274 87/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 19691703 m, 76866 m/sec, 52800192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1107 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 260/274 89/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 20075056 m, 76670 m/sec, 53635104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1112 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 265/274 91/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 20458021 m, 76593 m/sec, 54463668 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1117 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 270/274 92/2000 SimpleLoadBal-PT-20-CTLFireability-2023-12 20840530 m, 76501 m/sec, 55287715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1122 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 37 (type EXCL) for SimpleLoadBal-PT-20-CTLFireability-2023-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1127 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 SimpleLoadBal-PT-20-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 274 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 SimpleLoadBal-PT-20-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 2473 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for SimpleLoadBal-PT-20-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 5/274 2/5 SimpleLoadBal-PT-20-CTLFireability-2023-12 380589 m, -4091988 m/sec, 1415537 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1132 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 10/274 4/5 SimpleLoadBal-PT-20-CTLFireability-2023-12 786923 m, 81266 m/sec, 2905698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1137 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 37 (type EXCL) for SimpleLoadBal-PT-20-CTLFireability-2023-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1142 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 SimpleLoadBal-PT-20-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 307 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 5/307 3/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 513205 m, 102641 m/sec, 2428223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1147 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 10/307 5/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 1063668 m, 110092 m/sec, 5000246 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1152 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 15/307 8/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 1609533 m, 109173 m/sec, 7453695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1157 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 20/307 10/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 2148516 m, 107796 m/sec, 9758315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1162 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 25/307 13/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 2661602 m, 102617 m/sec, 12002563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1167 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 30/307 15/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 3176654 m, 103010 m/sec, 14207972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1172 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 35/307 17/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 3689097 m, 102488 m/sec, 16447675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1177 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 40/307 20/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 4213317 m, 104844 m/sec, 18653400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1182 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 45/307 22/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 4726453 m, 102627 m/sec, 20856149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1187 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 50/307 24/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 5279361 m, 110581 m/sec, 22846561 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1192 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 55/307 27/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 5813232 m, 106774 m/sec, 24820325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1197 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 60/307 29/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 6328275 m, 103008 m/sec, 26890893 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1202 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 65/307 31/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 6860081 m, 106361 m/sec, 28855753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1207 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 70/307 34/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 7401933 m, 108370 m/sec, 30819105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1212 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 75/307 36/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 7952103 m, 110034 m/sec, 32616655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1217 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 80/307 38/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 8475915 m, 104762 m/sec, 34581085 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1222 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 85/307 41/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 9026008 m, 110018 m/sec, 36415306 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1227 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 90/307 43/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 9562546 m, 107307 m/sec, 38316277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1232 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 95/307 45/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 10103383 m, 108167 m/sec, 40131440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1237 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 100/307 48/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 10625782 m, 104479 m/sec, 42008114 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1242 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 105/307 50/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 11158135 m, 106470 m/sec, 43834433 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1247 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 110/307 52/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 11691716 m, 106716 m/sec, 45637300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1252 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 115/307 55/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 12217915 m, 105239 m/sec, 47406323 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1257 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 120/307 57/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 12743032 m, 105023 m/sec, 49265744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1262 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 125/307 59/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 13273568 m, 106107 m/sec, 51049431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1267 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 130/307 61/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 13793879 m, 104062 m/sec, 52808126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1272 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 135/307 64/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 14321233 m, 105470 m/sec, 54569207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1277 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 140/307 66/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 14845605 m, 104874 m/sec, 56350879 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1282 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 145/307 68/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 15336504 m, 98179 m/sec, 58137727 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1287 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 150/307 71/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 15863026 m, 105304 m/sec, 59801513 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1292 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 155/307 73/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 16371679 m, 101730 m/sec, 61595936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1297 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 160/307 75/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 16885834 m, 102831 m/sec, 63392999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1302 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 165/307 77/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 17405557 m, 103944 m/sec, 65055638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1307 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 170/307 79/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 17882371 m, 95362 m/sec, 66619808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1312 secs. Pages in use: 264
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 175/307 82/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 18392701 m, 102066 m/sec, 68288077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1317 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 180/307 84/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 18906059 m, 102671 m/sec, 69953977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1322 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 185/307 86/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 19417382 m, 102264 m/sec, 71631916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1327 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 190/307 88/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 19929504 m, 102424 m/sec, 73252596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1332 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 195/307 90/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 20443129 m, 102725 m/sec, 74873719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1337 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 200/307 92/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 20772308 m, 65835 m/sec, 75914298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1342 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 205/307 92/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 20772308 m, 0 m/sec, 75914298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1347 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 210/307 92/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 20772308 m, 0 m/sec, 75914298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1352 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 215/307 92/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 20772308 m, 0 m/sec, 75914298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1357 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 220/307 92/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 20772308 m, 0 m/sec, 75914298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1362 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 225/307 92/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 20772308 m, 0 m/sec, 75914298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1367 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 230/307 92/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 20772308 m, 0 m/sec, 75914298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1372 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 235/307 92/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 20825787 m, 10695 m/sec, 76025390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1377 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 240/307 96/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 21642895 m, 163421 m/sec, 77213675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1382 secs. Pages in use: 281
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2024-00: AG true state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-07: EU false state equation[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-20-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-20-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] SimpleLoadBal-PT-20-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 245/307 99/2000 SimpleLoadBal-PT-20-CTLFireability-2024-10 22483833 m, 168187 m/sec, 78384276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1387 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SimpleLoadBal-PT-20"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is SimpleLoadBal-PT-20, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r379-smll-171683812000178"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SimpleLoadBal-PT-20.tgz
mv SimpleLoadBal-PT-20 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;