About the Execution of LoLA for SimpleLoadBal-PT-15
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 952.588 | 260763.00 | 745084.00 | 965.00 | FFFFTFFTFFFTTTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r379-smll-171683812000171.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is SimpleLoadBal-PT-15, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r379-smll-171683812000171
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.6M
-rw-r--r-- 1 mcc users 8.4K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.0K Apr 23 07:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 23 07:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Apr 23 07:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 91K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 13 12:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K Apr 13 12:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 23 07:57 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:57 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 1.2M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-00
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-01
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-02
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-03
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-04
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-05
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-06
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-07
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-08
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-09
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-10
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-11
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-12
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-13
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-14
FORMULA_NAME SimpleLoadBal-PT-15-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717116364881
FORMULA SimpleLoadBal-PT-15-LTLCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-15-LTLCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mSimpleLoadBal-PT-15-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-06: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mSimpleLoadBal-PT-15-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-09: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[32mSimpleLoadBal-PT-15-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m] [1m[32mSimpleLoadBal-PT-15-LTLCardinality-12: AR true state space /EU[0m
[[35mlola[0m] [1m[32mSimpleLoadBal-PT-15-LTLCardinality-13: F true state space / EG[0m
[[35mlola[0m] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 261 secs. Pages in use: 4
BK_STOP 1717116625644
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 21 (type CNST) for 20 SimpleLoadBal-PT-15-LTLCardinality-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 21 (type CNST) for SimpleLoadBal-PT-15-LTLCardinality-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 40 (type CNST) for 39 SimpleLoadBal-PT-15-LTLCardinality-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 40 (type CNST) for SimpleLoadBal-PT-15-LTLCardinality-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 61 (type CNST) for 54 SimpleLoadBal-PT-15-LTLCardinality-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 61 (type CNST) for SimpleLoadBal-PT-15-LTLCardinality-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 24 (type CNST) for 23 SimpleLoadBal-PT-15-LTLCardinality-05
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 43 (type CNST) for 42 SimpleLoadBal-PT-15-LTLCardinality-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 43 (type CNST) for SimpleLoadBal-PT-15-LTLCardinality-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 24 (type CNST) for SimpleLoadBal-PT-15-LTLCardinality-05
[[35mlola[0m][I] result : false
[*** LOG ERROR #0001 ***] [2024-05-31 00:46:24] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 12 (type EXCL) for 3 SimpleLoadBal-PT-15-LTLCardinality-01
[[35mlola[0m][I] time limit : 255 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 12 (type EXCL) for SimpleLoadBal-PT-15-LTLCardinality-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 48
[[35mlola[0m][I] fired transitions : 48
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 SimpleLoadBal-PT-15-LTLCardinality-11
[[35mlola[0m][I] time limit : 325 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for SimpleLoadBal-PT-15-LTLCardinality-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 16
[[35mlola[0m][I] fired transitions : 15
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 18 (type EXCL) for 17 SimpleLoadBal-PT-15-LTLCardinality-03
[[35mlola[0m][I] time limit : 357 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 73 (type FNDP) for 26 SimpleLoadBal-PT-15-LTLCardinality-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 26 SimpleLoadBal-PT-15-LTLCardinality-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 80 (type EQUN) for 51 SimpleLoadBal-PT-15-LTLCardinality-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for SimpleLoadBal-PT-15-LTLCardinality-06
[[35mlola[0m][I] result : false
[[35mlola[0m][W] CANCELED task # 73 (type FNDP) for SimpleLoadBal-PT-15-LTLCardinality-06 (obsolete)
[[35mlola[0m][I] LAUNCH task # 84 (type EQUN) for 48 SimpleLoadBal-PT-15-LTLCardinality-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 80 (type EQUN) for SimpleLoadBal-PT-15-LTLCardinality-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-15-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-15-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 2
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-12: AR 0 1 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 18 LTL EXCL 3/397 1/2000 SimpleLoadBal-PT-15-LTLCardinality-03 14602 m, 2920 m/sec, 22529 t fired, .
[[35mlola[0m][.] 84 EF STEQ 3/3579 0/5 SimpleLoadBal-PT-15-LTLCardinality-12 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 24 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-15-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-15-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 2
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-12: AR 0 1 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 18 LTL EXCL 8/397 1/2000 SimpleLoadBal-PT-15-LTLCardinality-03 33109 m, 3701 m/sec, 52102 t fired, .
[[35mlola[0m][.] 84 EF STEQ 8/3579 0/5 SimpleLoadBal-PT-15-LTLCardinality-12 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 29 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-15-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mSimpleLoadBal-PT-15-LTLCardinality-11: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mSimpleLoadBal-PT-15-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 2
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-12: AR 0 1 1 0 1 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] SimpleLoadBal-PT-15-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 18 LTL EXCL 13/397 1/2000 SimpleLoadBal-PT-15-LTLCardinality-03 51737 m, 3725 m/sec, 82244 t fired, .
[[35mlola[0m][.] 84 EF STEQ 13/3579 0/5 SimpleLoadBal-PT-15-LTLCardinality-12 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 34 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 18 (type EXCL) for SimpleLoadBal-PT-15-LTLCardinality-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 67203
[[35mlola[0m][I] fired transitions : 107815
[[35mlola[0m][I] time used : 18
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 66 (type EXCL) for 65 SimpleLoadBal-PT-15-LTLCardinality-15
[[35mlola[0m][I] time limit : 445 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 66 (type EXCL) for SimpleLoadBal-PT-15-LTLCardinality-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 49
[[35mlola[0m][I] fired transitions : 50
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
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[[35mlola[0m][.] 37 LTL EXCL 45/1187 1/2000 SimpleLoadBal-PT-15-LTLCardinality-08 111314 m, 2511 m/sec, 134028 t fired, .
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[[35mlola[0m][.] 37 LTL EXCL 210/1187 4/2000 SimpleLoadBal-PT-15-LTLCardinality-08 513339 m, 2403 m/sec, 654429 t fired, .
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[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SimpleLoadBal-PT-15"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is SimpleLoadBal-PT-15, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r379-smll-171683812000171"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SimpleLoadBal-PT-15.tgz
mv SimpleLoadBal-PT-15 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;