fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r379-smll-171683812000156
Last Updated
July 7, 2024

About the Execution of LoLA for SimpleLoadBal-PT-05

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
222.588 4552.00 4302.00 84.90 FFFFFFTFTTFFTFTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r379-smll-171683812000156.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is SimpleLoadBal-PT-05, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r379-smll-171683812000156
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 768K
-rw-r--r-- 1 mcc users 8.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.7K Apr 23 07:56 LTLCardinality.txt
-rw-r--r-- 1 mcc users 32K Apr 23 07:56 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.3K Apr 23 07:56 LTLFireability.txt
-rw-r--r-- 1 mcc users 22K Apr 23 07:56 LTLFireability.xml
-rw-r--r-- 1 mcc users 23K Apr 13 12:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 196K Apr 13 12:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 17K Apr 13 12:08 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 107K Apr 13 12:08 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 07:56 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:56 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 155K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-00
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-01
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-02
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-03
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-04
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-05
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-06
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-07
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-08
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-09
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-10
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-11
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-12
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-13
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-14
FORMULA_NAME SimpleLoadBal-PT-05-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717110718111

FORMULA SimpleLoadBal-PT-05-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SimpleLoadBal-PT-05-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] SimpleLoadBal-PT-05-LTLFireability-00: LTL false LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-01: LTL false LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-02: LTL false LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-03: LTL false LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-04: CONJ false LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-05: CONJ false LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-06: LTL true LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-07: CONJ false LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-08: LTL true LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-09: LTL true LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-10: LTL false LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-11: LTL false LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-12: LTL true LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-13: LTL false LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-14: LTL true LTL model checker
[lola] SimpleLoadBal-PT-05-LTLFireability-15: LTL true LTL model checker
[lola]
[lola] Time elapsed: 4 secs. Pages in use: 3

BK_STOP 1717110722663

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 36 (type CNST) for 33 SimpleLoadBal-PT-05-LTLFireability-07
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 36 (type CNST) for SimpleLoadBal-PT-05-LTLFireability-07
[lola][I] result : true
[lola][I] LAUNCH task # 21 (type EXCL) for 12 SimpleLoadBal-PT-05-LTLFireability-04
[lola][I] time limit : 171 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 21 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-04
[lola][I] result : true
[lola][I] markings : 232352
[lola][I] fired transitions : 1127744
[lola][I] time used : 1
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 62 (type EXCL) for 61 SimpleLoadBal-PT-05-LTLFireability-15
[lola][I] time limit : 199 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 62 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-15
[lola][I] result : true
[lola][I] markings : 41
[lola][I] fired transitions : 60
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 59 (type EXCL) for 58 SimpleLoadBal-PT-05-LTLFireability-14
[lola][I] time limit : 211 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 59 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-14
[lola][I] result : true
[lola][I] markings : 11
[lola][I] fired transitions : 10
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 56 (type EXCL) for 55 SimpleLoadBal-PT-05-LTLFireability-13
[lola][I] time limit : 224 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 56 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-13
[lola][I] result : false
[lola][I] markings : 37
[lola][I] fired transitions : 38
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 53 (type EXCL) for 52 SimpleLoadBal-PT-05-LTLFireability-12
[lola][I] time limit : 239 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 53 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-12
[lola][I] result : true
[lola][I] markings : 348619
[lola][I] fired transitions : 1706926
[lola][I] time used : 1
[lola][I] memory pages used : 3
[lola][I] LAUNCH task # 50 (type EXCL) for 49 SimpleLoadBal-PT-05-LTLFireability-11
[lola][I] time limit : 257 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 50 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-11
[lola][I] result : false
[lola][I] markings : 31
[lola][I] fired transitions : 31
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 47 (type EXCL) for 46 SimpleLoadBal-PT-05-LTLFireability-10
[lola][I] time limit : 276 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 47 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-10
[lola][I] result : false
[lola][I] markings : 36
[lola][I] fired transitions : 36
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 44 (type EXCL) for 43 SimpleLoadBal-PT-05-LTLFireability-09
[lola][I] time limit : 299 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 44 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-09
[lola][I] result : true
[lola][I] markings : 21
[lola][I] fired transitions : 30
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 41 (type EXCL) for 40 SimpleLoadBal-PT-05-LTLFireability-08
[lola][I] time limit : 327 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 41 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-08
[lola][I] result : true
[lola][I] markings : 348528
[lola][I] fired transitions : 2265328
[lola][I] time used : 2
[lola][I] memory pages used : 3
[lola][I] LAUNCH task # 38 (type EXCL) for 33 SimpleLoadBal-PT-05-LTLFireability-07
[lola][I] time limit : 359 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 38 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-07
[lola][I] result : false
[lola][I] markings : 37
[lola][I] fired transitions : 38
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 26 (type EXCL) for 23 SimpleLoadBal-PT-05-LTLFireability-05
[lola][I] time limit : 399 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 26 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-05
[lola][I] result : false
[lola][I] markings : 36
[lola][I] fired transitions : 36
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 19 (type EXCL) for 12 SimpleLoadBal-PT-05-LTLFireability-04
[lola][I] time limit : 513 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 19 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-04
[lola][I] result : false
[lola][I] markings : 36
[lola][I] fired transitions : 36
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 10 (type EXCL) for 9 SimpleLoadBal-PT-05-LTLFireability-03
[lola][I] time limit : 719 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 10 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-03
[lola][I] result : false
[lola][I] markings : 36
[lola][I] fired transitions : 36
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 7 (type EXCL) for 6 SimpleLoadBal-PT-05-LTLFireability-02
[lola][I] time limit : 899 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 7 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-02
[lola][I] result : false
[lola][I] markings : 36
[lola][I] fired transitions : 36
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 4 (type EXCL) for 3 SimpleLoadBal-PT-05-LTLFireability-01
[lola][I] time limit : 1198 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 4 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-01
[lola][I] result : false
[lola][I] markings : 38
[lola][I] fired transitions : 39
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 1 (type EXCL) for 0 SimpleLoadBal-PT-05-LTLFireability-00
[lola][I] time limit : 1798 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-00
[lola][I] result : false
[lola][I] markings : 20
[lola][I] fired transitions : 21
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 31 (type EXCL) for 30 SimpleLoadBal-PT-05-LTLFireability-06
[lola][I] time limit : 3596 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 31 (type EXCL) for SimpleLoadBal-PT-05-LTLFireability-06
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SimpleLoadBal-PT-05"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is SimpleLoadBal-PT-05, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r379-smll-171683812000156"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SimpleLoadBal-PT-05.tgz
mv SimpleLoadBal-PT-05 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;