Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r377-smll-171683810000258.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool greatspnxred
Input is SmallOperatingSystem-PT-MT0512DC0128, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r377-smll-171683810000258
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 520K
-rw-r--r-- 1 mcc users 9.1K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Apr 23 07:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 23 07:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Apr 23 07:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 23 07:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Apr 12 14:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 147K Apr 12 14:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.5K Apr 12 14:07 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Apr 12 14:07 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 23 07:57 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Apr 23 07:57 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 13 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 8.2K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-00
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-01
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-02
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-03
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-04
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-05
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-06
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-07
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-08
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-09
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-10
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-11
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2023-12
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2023-13
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2023-14
FORMULA_NAME SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1716951825150

Invoking MCC driver with
BK_TOOL=greatspnxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT0512DC0128
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool greatspn
Invoking reducer
Running Version 202405141337
[2024-05-29 03:03:46] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-05-29 03:03:47] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-29 03:03:47] [INFO ] Load time of PNML (sax parser for PT used): 149 ms
[2024-05-29 03:03:47] [INFO ] Transformed 9 places.
[2024-05-29 03:03:47] [INFO ] Transformed 8 transitions.
[2024-05-29 03:03:47] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 337 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 27 ms.
Initial state reduction rules removed 2 formulas.
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2023-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2023-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 12 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2024-05-29 03:03:47] [INFO ] Computed 4 invariants in 5 ms
[2024-05-29 03:03:47] [INFO ] Implicit Places using invariants in 174 ms returned []
[2024-05-29 03:03:47] [INFO ] Invariant cache hit.
[2024-05-29 03:03:47] [INFO ] Implicit Places using invariants and state equation in 43 ms returned []
Implicit Place search using SMT with State Equation took 281 ms to find 0 implicit places.
Running 7 sub problems to find dead transitions.
[2024-05-29 03:03:47] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/8 variables, 3/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/8 variables, 0/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 2 (OVERLAPS) 1/9 variables, 1/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 4 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/17 variables, 0/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 6 (OVERLAPS) 0/17 variables, 0/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
No progress, stopping.
After SMT solving in domain Real declared 17/17 variables, and 13 constraints, problems are : Problem set: 0 solved, 7 unsolved in 209 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 7/7 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 7 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/8 variables, 3/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/8 variables, 0/3 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 2 (OVERLAPS) 1/9 variables, 1/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/9 variables, 0/4 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 4 (OVERLAPS) 8/17 variables, 9/13 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/17 variables, 7/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/17 variables, 0/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
At refinement iteration 7 (OVERLAPS) 0/17 variables, 0/20 constraints. Problems are: Problem set: 0 solved, 7 unsolved
No progress, stopping.
After SMT solving in domain Int declared 17/17 variables, and 20 constraints, problems are : Problem set: 0 solved, 7 unsolved in 219 ms.
Refiners :[Positive P Invariants (semi-flows): 4/4 constraints, State Equation: 9/9 constraints, PredecessorRefiner: 7/7 constraints, Known Traps: 0/0 constraints]
After SMT, in 461ms problems are : Problem set: 0 solved, 7 unsolved
Search for dead transitions found 0 dead transitions in 474ms
Finished structural reductions in LTL mode , in 1 iterations and 794 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 19 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 6 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 8 transitions.
Reduction of identical properties reduced properties to check from 23 to 22
RANDOM walk for 32239 steps (6 resets) in 143 ms. (223 steps per ms) remains 0/22 properties
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 3 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 3 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 15 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 7/9 places, 7/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 2 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 7/9 places, 7/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 2 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 7/9 places, 7/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 5 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 9/9 places, 8/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 2 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 8/9 places, 7/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 1 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Input system was already deterministic with 8 transitions.
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 2 ms
[2024-05-29 03:03:48] [INFO ] Flatten gal took : 3 ms
[2024-05-29 03:03:48] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2024-05-29 03:03:48] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 5 ms.
Total runtime 1979 ms.
There are residual formulas that ITS could not solve within timeout
----------------------------------------------------------------------
GreatSPN-meddly tool, MCC 2023
----------------------------------------------------------------------

Running SmallOperatingSystem-PT-MT0512DC0128

IS_COLORED=
IS_NUPN=

LOADING PETRI NET FILE /home/mcc/execution/415/model.pnml (PNML) ...
PNML VERSION 2009, P/T NET.
COLOR CLASSES: 0
CONSTANTS: 0
PLACES: 9
TRANSITIONS: 8
COLOR VARS: 0
MEASURES: 0
LOADING TIME: [User 0.000s, Sys 0.001s]


SAVING FILE /home/mcc/execution/415/model (.net / .def) ...
EXPORT TIME: [User 0.000s, Sys 0.000s]


----------------------------------------------------------------------
GreatSPN/Meddly.
Copyright (C) 1987-2022, University of Torino, Italy.
website: https://github.com/greatspn/SOURCES

Based on MEDDLY version 0.16.0
Copyright (C) 2009, Iowa State University Research Foundation, Inc.
website: http://meddly.sourceforge.net

Process ID: 536
MODEL NAME: /home/mcc/execution/415/model
9 places, 8 transitions.

Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Building monolithic NSF...
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-00 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-04 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-03 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-08 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-06 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-10 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2023-12 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-05 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-07 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-11 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2023-14 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-01 CANNOT_COMPUTE
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-02 CANNOT_COMPUTE
FORMULA SmallOperatingSystem-PT-MT0512DC0128-CTLFireability-2024-09 CANNOT_COMPUTE
Ok.
EXITCODE: 0
----------------------------------------------------------------------

BK_STOP 1716952631853

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
MEDDLY ERROR: Insufficient memory

MEDDLY ERROR: Insufficient memory

MEDDLY ERROR: Insufficient memory

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT0512DC0128"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="greatspnxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool greatspnxred"
echo " Input is SmallOperatingSystem-PT-MT0512DC0128, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r377-smll-171683810000258"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT0512DC0128.tgz
mv SmallOperatingSystem-PT-MT0512DC0128 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;