About the Execution of LoLA for ShieldRVt-PT-050B
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16208.331 | 322045.00 | 319237.00 | 1761.50 | F?T?F????F??T?F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r357-tall-171683764701036.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ShieldRVt-PT-050B, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r357-tall-171683764701036
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 7.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:56 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 07:56 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:33 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 19:17 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 11 21:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 168K Apr 11 21:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Apr 11 21:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 83K Apr 11 21:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 07:56 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:56 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 614K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-00
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-01
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-02
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-03
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-04
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-05
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-06
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-07
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-08
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-09
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-10
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-11
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-12
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-13
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-14
FORMULA_NAME ShieldRVt-PT-050B-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717206311130
FORMULA ShieldRVt-PT-050B-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-050B-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-050B-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-050B-LTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-050B-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-050B-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717206633175
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 19 (type CNST) for 16 ShieldRVt-PT-050B-LTLFireability-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 19 (type CNST) for ShieldRVt-PT-050B-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 3 (type EXCL) for 0 ShieldRVt-PT-050B-LTLFireability-00
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 3 (type EXCL) for ShieldRVt-PT-050B-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[*** LOG ERROR #0001 ***] [2024-06-01 01:45:11] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 ShieldRVt-PT-050B-LTLFireability-09
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for ShieldRVt-PT-050B-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 51
[[35mlola[0m][I] fired transitions : 63
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 ShieldRVt-PT-050B-LTLFireability-02
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type FNDP) for 54 ShieldRVt-PT-050B-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 54 ShieldRVt-PT-050B-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for ShieldRVt-PT-050B-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 54 ShieldRVt-PT-050B-LTLFireability-14
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 65 (type FNDP) for ShieldRVt-PT-050B-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 66 (type EQUN) for ShieldRVt-PT-050B-LTLFireability-14 (obsolete)
[[35mlola[0m][W] CANCELED task # 67 (type EXCL) for ShieldRVt-PT-050B-LTLFireability-14 (obsolete)
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 48 ShieldRVt-PT-050B-LTLFireability-12
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 49 (type EXCL) for ShieldRVt-PT-050B-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for ShieldRVt-PT-050B-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 ShieldRVt-PT-050B-LTLFireability-06
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 66 (type EQUN) for ShieldRVt-PT-050B-LTLFireability-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 3/327 6/2000 ShieldRVt-PT-050B-LTLFireability-06 730469 m, 146093 m/sec, 1216078 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 8/327 15/2000 ShieldRVt-PT-050B-LTLFireability-06 1821766 m, 218259 m/sec, 3223213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 13/327 24/2000 ShieldRVt-PT-050B-LTLFireability-06 2965973 m, 228841 m/sec, 5266921 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 18/327 33/2000 ShieldRVt-PT-050B-LTLFireability-06 4110612 m, 228927 m/sec, 7275793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 23/327 42/2000 ShieldRVt-PT-050B-LTLFireability-06 5196280 m, 217133 m/sec, 9267961 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 28/327 51/2000 ShieldRVt-PT-050B-LTLFireability-06 6413544 m, 243452 m/sec, 11204221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 33/327 60/2000 ShieldRVt-PT-050B-LTLFireability-06 7564584 m, 230208 m/sec, 13060498 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 38/327 69/2000 ShieldRVt-PT-050B-LTLFireability-06 8651580 m, 217399 m/sec, 14916526 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 43/327 75/2000 ShieldRVt-PT-050B-LTLFireability-06 9477227 m, 165129 m/sec, 16678585 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 48/327 82/2000 ShieldRVt-PT-050B-LTLFireability-06 10318349 m, 168224 m/sec, 18526569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 53/327 91/2000 ShieldRVt-PT-050B-LTLFireability-06 11467201 m, 229770 m/sec, 20573656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 58/327 100/2000 ShieldRVt-PT-050B-LTLFireability-06 12581132 m, 222786 m/sec, 22556987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 63/327 109/2000 ShieldRVt-PT-050B-LTLFireability-06 13674749 m, 218723 m/sec, 24564868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 68/327 118/2000 ShieldRVt-PT-050B-LTLFireability-06 14797028 m, 224455 m/sec, 26561193 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 73/327 127/2000 ShieldRVt-PT-050B-LTLFireability-06 15959663 m, 232527 m/sec, 28553371 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 78/327 136/2000 ShieldRVt-PT-050B-LTLFireability-06 17105326 m, 229132 m/sec, 30413868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 83/327 144/2000 ShieldRVt-PT-050B-LTLFireability-06 18180966 m, 215128 m/sec, 32225264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 88/327 152/2000 ShieldRVt-PT-050B-LTLFireability-06 19211282 m, 206063 m/sec, 34096762 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 93/327 158/2000 ShieldRVt-PT-050B-LTLFireability-06 19966959 m, 151135 m/sec, 35805257 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 98/327 167/2000 ShieldRVt-PT-050B-LTLFireability-06 21009867 m, 208581 m/sec, 37782946 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 103/327 175/2000 ShieldRVt-PT-050B-LTLFireability-06 22114248 m, 220876 m/sec, 39806974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 108/327 184/2000 ShieldRVt-PT-050B-LTLFireability-06 23248988 m, 226948 m/sec, 41829633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 113/327 193/2000 ShieldRVt-PT-050B-LTLFireability-06 24366384 m, 223479 m/sec, 43816593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 118/327 202/2000 ShieldRVt-PT-050B-LTLFireability-06 25470337 m, 220790 m/sec, 45815940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 123/327 212/2000 ShieldRVt-PT-050B-LTLFireability-06 26683167 m, 242566 m/sec, 47746158 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 128/327 221/2000 ShieldRVt-PT-050B-LTLFireability-06 27836795 m, 230725 m/sec, 49609696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 133/327 229/2000 ShieldRVt-PT-050B-LTLFireability-06 28928797 m, 218400 m/sec, 51477596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 138/327 236/2000 ShieldRVt-PT-050B-LTLFireability-06 29735647 m, 161370 m/sec, 53226105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 143/327 242/2000 ShieldRVt-PT-050B-LTLFireability-06 30595266 m, 171923 m/sec, 55090068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 148/327 252/2000 ShieldRVt-PT-050B-LTLFireability-06 31741508 m, 229248 m/sec, 57122120 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 153/327 260/2000 ShieldRVt-PT-050B-LTLFireability-06 32830447 m, 217787 m/sec, 59083734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 158/327 269/2000 ShieldRVt-PT-050B-LTLFireability-06 33932211 m, 220352 m/sec, 61094224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 163/327 278/2000 ShieldRVt-PT-050B-LTLFireability-06 35052756 m, 224109 m/sec, 63079725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 168/327 287/2000 ShieldRVt-PT-050B-LTLFireability-06 36205307 m, 230510 m/sec, 65055979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 287
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 173/327 296/2000 ShieldRVt-PT-050B-LTLFireability-06 37359085 m, 230755 m/sec, 66931633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 178/327 305/2000 ShieldRVt-PT-050B-LTLFireability-06 38427754 m, 213733 m/sec, 68733421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 183/327 313/2000 ShieldRVt-PT-050B-LTLFireability-06 39456133 m, 205675 m/sec, 70610155 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 188/327 319/2000 ShieldRVt-PT-050B-LTLFireability-06 40225340 m, 153841 m/sec, 72352792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 319
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 193/327 327/2000 ShieldRVt-PT-050B-LTLFireability-06 41267561 m, 208444 m/sec, 74322014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 198/327 336/2000 ShieldRVt-PT-050B-LTLFireability-06 42376517 m, 221791 m/sec, 76349124 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 203/327 345/2000 ShieldRVt-PT-050B-LTLFireability-06 43514358 m, 227568 m/sec, 78364179 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 345
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 208/327 353/2000 ShieldRVt-PT-050B-LTLFireability-06 44611671 m, 219462 m/sec, 80333475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 353
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 213/327 362/2000 ShieldRVt-PT-050B-LTLFireability-06 45732066 m, 224079 m/sec, 82339121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 362
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 218/327 372/2000 ShieldRVt-PT-050B-LTLFireability-06 46949094 m, 243405 m/sec, 84282706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 372
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 223/327 381/2000 ShieldRVt-PT-050B-LTLFireability-06 48104891 m, 231159 m/sec, 86152149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 381
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 228/327 390/2000 ShieldRVt-PT-050B-LTLFireability-06 49195505 m, 218122 m/sec, 88023794 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 390
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 233/327 396/2000 ShieldRVt-PT-050B-LTLFireability-06 50001150 m, 161129 m/sec, 89789633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 396
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 238/327 403/2000 ShieldRVt-PT-050B-LTLFireability-06 50903399 m, 180449 m/sec, 91703296 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 403
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 243/327 413/2000 ShieldRVt-PT-050B-LTLFireability-06 52031241 m, 225568 m/sec, 93725503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 248/327 422/2000 ShieldRVt-PT-050B-LTLFireability-06 53103378 m, 214427 m/sec, 95666464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 422
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 253/327 431/2000 ShieldRVt-PT-050B-LTLFireability-06 54242567 m, 227837 m/sec, 97683423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 431
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 258/327 439/2000 ShieldRVt-PT-050B-LTLFireability-06 55319602 m, 215407 m/sec, 99666477 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 439
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 263/327 448/2000 ShieldRVt-PT-050B-LTLFireability-06 56454951 m, 227069 m/sec, 101676195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 448
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 268/327 457/2000 ShieldRVt-PT-050B-LTLFireability-06 57537956 m, 216601 m/sec, 103638450 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 457
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 273/327 466/2000 ShieldRVt-PT-050B-LTLFireability-06 58731101 m, 238629 m/sec, 105581946 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 466
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 278/327 475/2000 ShieldRVt-PT-050B-LTLFireability-06 59847038 m, 223187 m/sec, 107416518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 475
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 283/327 483/2000 ShieldRVt-PT-050B-LTLFireability-06 60904285 m, 211449 m/sec, 109241715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 483
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 288/327 490/2000 ShieldRVt-PT-050B-LTLFireability-06 61801355 m, 179414 m/sec, 111041660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 490
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 293/327 496/2000 ShieldRVt-PT-050B-LTLFireability-06 62569170 m, 153563 m/sec, 112788144 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 496
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 298/327 506/2000 ShieldRVt-PT-050B-LTLFireability-06 63733194 m, 232804 m/sec, 114812687 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 506
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 304/327 511/2000 ShieldRVt-PT-050B-LTLFireability-06 64468028 m, 146966 m/sec, 116120273 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 511
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-050B-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-050B-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-050B-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 318/327 512/2000 ShieldRVt-PT-050B-LTLFireability-06 64512412 m, 8876 m/sec, 116195586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 512
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ShieldRVt-PT-050B"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ShieldRVt-PT-050B, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r357-tall-171683764701036"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ShieldRVt-PT-050B.tgz
mv ShieldRVt-PT-050B execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;