About the Execution of LoLA for ShieldRVt-PT-004A
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 323.899 | 11836.00 | 12384.00 | 100.10 | FTFFTTTTFFFTTTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r357-tall-171683764500930.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ShieldRVt-PT-004A, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r357-tall-171683764500930
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 504K
-rw-r--r-- 1 mcc users 6.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 64K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:55 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Apr 23 07:55 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 23 07:55 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 23 07:55 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 11 21:15 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 148K Apr 11 21:15 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.6K Apr 11 21:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K Apr 11 21:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 07:55 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:55 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 12K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-00
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-01
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-02
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-03
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-04
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-05
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-06
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-07
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-08
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-09
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-10
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2024-11
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2023-12
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2023-13
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2023-14
FORMULA_NAME ShieldRVt-PT-004A-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717198353169
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVt-PT-004A-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-04: DISJ true CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-06: AGEF true tscc_search[0m
[[35mlola[0m] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVt-PT-004A-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVt-PT-004A-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mShieldRVt-PT-004A-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mShieldRVt-PT-004A-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 11 secs. Pages in use: 1
BK_STOP 1717198365005
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 ShieldRVt-PT-004A-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 119 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type FNDP) for 12 ShieldRVt-PT-004A-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 12 ShieldRVt-PT-004A-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type FNDP) for ShieldRVt-PT-004A-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 66 (type EQUN) for ShieldRVt-PT-004A-CTLFireability-2024-04 (obsolete)
[[35mlola[0m][I] FINISHED task # 66 (type EQUN) for ShieldRVt-PT-004A-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 26 ShieldRVt-PT-004A-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 26 ShieldRVt-PT-004A-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 71 (type EQUN) for ShieldRVt-PT-004A-CTLFireability-2024-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 73 (type EQUN) for ShieldRVt-PT-004A-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 131073
[[35mlola[0m][I] fired transitions : 1425409
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 61 ShieldRVt-PT-004A-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 58 ShieldRVt-PT-004A-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 56 (type EXCL) for 55 ShieldRVt-PT-004A-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 56 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 52 ShieldRVt-PT-004A-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 ShieldRVt-PT-004A-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 131072
[[35mlola[0m][I] fired transitions : 1490944
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 38 ShieldRVt-PT-004A-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 14
[[35mlola[0m][I] fired transitions : 34
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 38 ShieldRVt-PT-004A-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 94208
[[35mlola[0m][I] fired transitions : 724996
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 ShieldRVt-PT-004A-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 131073
[[35mlola[0m][I] fired transitions : 1947769
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 ShieldRVt-PT-004A-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 49
[[35mlola[0m][I] fired transitions : 83
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 ShieldRVt-PT-004A-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 131073
[[35mlola[0m][I] fired transitions : 1706367
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 23 ShieldRVt-PT-004A-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-004A-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-004A-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-004A-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-004A-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-004A-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-004A-CTLFireability-2024-04: DISJ 0 2 0 0 5 0 0 1
[[35mlola[0m][.] ShieldRVt-PT-004A-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVt-PT-004A-CTLFireability-2024-06: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 1/513 1/2000 ShieldRVt-PT-004A-CTLFireability-2024-05 109516 m, 21903 m/sec, 868479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 24 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 131073
[[35mlola[0m][I] fired transitions : 1900654
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 21 (type EXCL) for 12 ShieldRVt-PT-004A-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 598 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 21 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 131072
[[35mlola[0m][I] fired transitions : 1687552
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 ShieldRVt-PT-004A-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 718 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 131073
[[35mlola[0m][I] fired transitions : 2449474
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 ShieldRVt-PT-004A-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 897 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 131073
[[35mlola[0m][I] fired transitions : 1605718
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 68 (type EXCL) for 26 ShieldRVt-PT-004A-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 1196 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 68 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 65537
[[35mlola[0m][I] fired transitions : 427157
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 12 ShieldRVt-PT-004A-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 1794 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 65537
[[35mlola[0m][I] fired transitions : 696323
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 ShieldRVt-PT-004A-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 3589 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-04: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-06: AGEF true tscc_search[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-004A-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-004A-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVt-PT-004A-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVt-PT-004A-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVt-PT-004A-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 0/3589 1/2000 ShieldRVt-PT-004A-CTLFireability-2024-01 1903 m, 380 m/sec, 7415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for ShieldRVt-PT-004A-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 65537
[[35mlola[0m][I] fired transitions : 794651
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ShieldRVt-PT-004A"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ShieldRVt-PT-004A, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r357-tall-171683764500930"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ShieldRVt-PT-004A.tgz
mv ShieldRVt-PT-004A execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;