About the Execution of LoLA for ShieldRVs-PT-040A
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16203.020 | 1615906.00 | 1624320.00 | 3703.70 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r357-tall-171683764300836.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ShieldRVs-PT-040A, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r357-tall-171683764300836
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 664K
-rw-r--r-- 1 mcc users 7.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 87K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K May 19 07:16 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 19 16:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:33 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 19:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.5K Apr 12 18:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 84K Apr 12 18:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Apr 12 17:59 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Apr 12 17:59 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 07:55 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:55 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 256K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-00
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-01
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-02
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-03
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-04
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-05
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-06
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-07
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-08
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-09
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-10
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-11
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-12
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-13
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-14
FORMULA_NAME ShieldRVs-PT-040A-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717183338235
BK_STOP 1717184954141
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 3 (type CNST) for 0 ShieldRVs-PT-040A-LTLFireability-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 3 (type CNST) for ShieldRVs-PT-040A-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 ShieldRVs-PT-040A-LTLFireability-11
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[*** LOG ERROR #0001 ***] [2024-05-31 19:22:33] [status_logger] string pointer is null
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3454
[[35mlola[0m][I] fired transitions : 3454
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 ShieldRVs-PT-040A-LTLFireability-12
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 4/239 4/2000 ShieldRVs-PT-040A-LTLFireability-12 405434 m, 81086 m/sec, 3139031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 19 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 9/239 8/2000 ShieldRVs-PT-040A-LTLFireability-12 802911 m, 79495 m/sec, 6638335 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 24 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 14/239 11/2000 ShieldRVs-PT-040A-LTLFireability-12 1182723 m, 75962 m/sec, 10119603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 29 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 19/239 14/2000 ShieldRVs-PT-040A-LTLFireability-12 1547438 m, 72943 m/sec, 13597911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 34 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 24/239 17/2000 ShieldRVs-PT-040A-LTLFireability-12 1904565 m, 71425 m/sec, 17068732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 39 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 29/239 21/2000 ShieldRVs-PT-040A-LTLFireability-12 2264984 m, 72083 m/sec, 20529024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 44 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 34/239 24/2000 ShieldRVs-PT-040A-LTLFireability-12 2631084 m, 73220 m/sec, 24004002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 49 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 39/239 27/2000 ShieldRVs-PT-040A-LTLFireability-12 2978611 m, 69505 m/sec, 27483223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 54 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 44/239 30/2000 ShieldRVs-PT-040A-LTLFireability-12 3324090 m, 69095 m/sec, 30962534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 59 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 49/239 33/2000 ShieldRVs-PT-040A-LTLFireability-12 3650382 m, 65258 m/sec, 34403805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 64 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 54/239 36/2000 ShieldRVs-PT-040A-LTLFireability-12 3969283 m, 63780 m/sec, 37864757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 69 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 59/239 39/2000 ShieldRVs-PT-040A-LTLFireability-12 4312512 m, 68645 m/sec, 41325247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 74 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 64/239 42/2000 ShieldRVs-PT-040A-LTLFireability-12 4679864 m, 73470 m/sec, 44824938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 79 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 69/239 45/2000 ShieldRVs-PT-040A-LTLFireability-12 5031027 m, 70232 m/sec, 48313857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 84 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 74/239 48/2000 ShieldRVs-PT-040A-LTLFireability-12 5380738 m, 69942 m/sec, 51833058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 89 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 79/239 51/2000 ShieldRVs-PT-040A-LTLFireability-12 5711191 m, 66090 m/sec, 55324460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 94 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 84/239 54/2000 ShieldRVs-PT-040A-LTLFireability-12 6031521 m, 64066 m/sec, 58793843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 99 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 89/239 57/2000 ShieldRVs-PT-040A-LTLFireability-12 6356366 m, 64969 m/sec, 62260560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 104 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 94/239 60/2000 ShieldRVs-PT-040A-LTLFireability-12 6688366 m, 66400 m/sec, 65736405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 109 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 99/239 63/2000 ShieldRVs-PT-040A-LTLFireability-12 7012643 m, 64855 m/sec, 69214097 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 114 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 104/239 66/2000 ShieldRVs-PT-040A-LTLFireability-12 7318424 m, 61156 m/sec, 72664798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 119 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 109/239 68/2000 ShieldRVs-PT-040A-LTLFireability-12 7628683 m, 62051 m/sec, 76115130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 124 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 114/239 71/2000 ShieldRVs-PT-040A-LTLFireability-12 7923965 m, 59056 m/sec, 79554848 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 129 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 119/239 73/2000 ShieldRVs-PT-040A-LTLFireability-12 8200865 m, 55380 m/sec, 82991813 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 134 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 124/239 77/2000 ShieldRVs-PT-040A-LTLFireability-12 8569095 m, 73646 m/sec, 86470091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 139 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 129/239 80/2000 ShieldRVs-PT-040A-LTLFireability-12 8931678 m, 72516 m/sec, 89950738 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 144 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 134/239 83/2000 ShieldRVs-PT-040A-LTLFireability-12 9265009 m, 66666 m/sec, 93434265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 149 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 139/239 86/2000 ShieldRVs-PT-040A-LTLFireability-12 9614873 m, 69972 m/sec, 96884590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 154 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 144/239 89/2000 ShieldRVs-PT-040A-LTLFireability-12 9939998 m, 65025 m/sec, 100345524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 159 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 149/239 92/2000 ShieldRVs-PT-040A-LTLFireability-12 10240433 m, 60087 m/sec, 103701539 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 164 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 154/239 94/2000 ShieldRVs-PT-040A-LTLFireability-12 10565589 m, 65031 m/sec, 107058059 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 169 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 159/239 97/2000 ShieldRVs-PT-040A-LTLFireability-12 10888866 m, 64655 m/sec, 110454600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 174 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 164/239 100/2000 ShieldRVs-PT-040A-LTLFireability-12 11199774 m, 62181 m/sec, 113846930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 179 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 169/239 103/2000 ShieldRVs-PT-040A-LTLFireability-12 11501364 m, 60318 m/sec, 117220108 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 184 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 174/239 105/2000 ShieldRVs-PT-040A-LTLFireability-12 11805725 m, 60872 m/sec, 120661150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 189 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 179/239 108/2000 ShieldRVs-PT-040A-LTLFireability-12 12098540 m, 58563 m/sec, 124093266 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 194 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 184/239 110/2000 ShieldRVs-PT-040A-LTLFireability-12 12368514 m, 53994 m/sec, 127484229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 199 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 189/239 114/2000 ShieldRVs-PT-040A-LTLFireability-12 12718646 m, 70026 m/sec, 130965475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 204 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 194/239 116/2000 ShieldRVs-PT-040A-LTLFireability-12 13044856 m, 65242 m/sec, 134436035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 209 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 199/239 119/2000 ShieldRVs-PT-040A-LTLFireability-12 13353688 m, 61766 m/sec, 137921823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 214 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 204/239 122/2000 ShieldRVs-PT-040A-LTLFireability-12 13668546 m, 62971 m/sec, 141388338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 219 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 209/239 125/2000 ShieldRVs-PT-040A-LTLFireability-12 13967031 m, 59697 m/sec, 144833129 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 224 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 214/239 127/2000 ShieldRVs-PT-040A-LTLFireability-12 14257746 m, 58143 m/sec, 148262193 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 229 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 219/239 130/2000 ShieldRVs-PT-040A-LTLFireability-12 14544659 m, 57382 m/sec, 151693938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 234 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 224/239 133/2000 ShieldRVs-PT-040A-LTLFireability-12 14852872 m, 61642 m/sec, 155122185 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 239 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 229/239 135/2000 ShieldRVs-PT-040A-LTLFireability-12 15146792 m, 58784 m/sec, 158544639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 244 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 234/239 138/2000 ShieldRVs-PT-040A-LTLFireability-12 15421752 m, 54992 m/sec, 161958574 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 249 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 239/239 140/2000 ShieldRVs-PT-040A-LTLFireability-12 15709390 m, 57527 m/sec, 165384802 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 254 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 45 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 259 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 ShieldRVs-PT-040A-LTLFireability-15
[[35mlola[0m][I] time limit : 238 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 ShieldRVs-PT-040A-LTLFireability-12
[[35mlola[0m][I] time limit : 3341 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3454
[[35mlola[0m][I] fired transitions : 3454
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 5/238 5/5 ShieldRVs-PT-040A-LTLFireability-12 452188 m, -3051440 m/sec, 3553754 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 264 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 45 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 269 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 ShieldRVs-PT-040A-LTLFireability-14
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 5/256 11/2000 ShieldRVs-PT-040A-LTLFireability-14 1267805 m, 253561 m/sec, 2914540 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 274 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 10/256 21/2000 ShieldRVs-PT-040A-LTLFireability-14 2410783 m, 228595 m/sec, 5794891 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 279 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 15/256 30/2000 ShieldRVs-PT-040A-LTLFireability-14 3508277 m, 219498 m/sec, 8646710 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 284 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 20/256 39/2000 ShieldRVs-PT-040A-LTLFireability-14 4573760 m, 213096 m/sec, 11486781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 289 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 25/256 47/2000 ShieldRVs-PT-040A-LTLFireability-14 5610786 m, 207405 m/sec, 14300882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 294 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 30/256 56/2000 ShieldRVs-PT-040A-LTLFireability-14 6637193 m, 205281 m/sec, 17110286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 299 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 35/256 65/2000 ShieldRVs-PT-040A-LTLFireability-14 7803667 m, 233294 m/sec, 19959791 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 304 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 40/256 75/2000 ShieldRVs-PT-040A-LTLFireability-14 8911476 m, 221561 m/sec, 22814073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 309 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 45/256 83/2000 ShieldRVs-PT-040A-LTLFireability-14 9935259 m, 204756 m/sec, 25637428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 314 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 50/256 91/2000 ShieldRVs-PT-040A-LTLFireability-14 10942971 m, 201542 m/sec, 28421765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 319 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 55/256 100/2000 ShieldRVs-PT-040A-LTLFireability-14 11992112 m, 209828 m/sec, 31210872 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 324 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 60/256 108/2000 ShieldRVs-PT-040A-LTLFireability-14 12988228 m, 199223 m/sec, 33966073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 329 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 65/256 117/2000 ShieldRVs-PT-040A-LTLFireability-14 13966227 m, 195599 m/sec, 36716796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 334 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 70/256 125/2000 ShieldRVs-PT-040A-LTLFireability-14 14930146 m, 192783 m/sec, 39444913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 339 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 75/256 133/2000 ShieldRVs-PT-040A-LTLFireability-14 15913331 m, 196637 m/sec, 42191215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 344 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 80/256 141/2000 ShieldRVs-PT-040A-LTLFireability-14 16893247 m, 195983 m/sec, 44926143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 349 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 85/256 149/2000 ShieldRVs-PT-040A-LTLFireability-14 17812630 m, 183876 m/sec, 47639401 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 354 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 90/256 156/2000 ShieldRVs-PT-040A-LTLFireability-14 18766880 m, 190850 m/sec, 50341629 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 359 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 95/256 164/2000 ShieldRVs-PT-040A-LTLFireability-14 19682759 m, 183175 m/sec, 52989416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 364 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 100/256 172/2000 ShieldRVs-PT-040A-LTLFireability-14 20612306 m, 185909 m/sec, 55661742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 369 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 105/256 180/2000 ShieldRVs-PT-040A-LTLFireability-14 21571713 m, 191881 m/sec, 58389917 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 374 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 110/256 187/2000 ShieldRVs-PT-040A-LTLFireability-14 22488149 m, 183287 m/sec, 61058829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 379 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 115/256 195/2000 ShieldRVs-PT-040A-LTLFireability-14 23417484 m, 185867 m/sec, 63730900 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 384 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 120/256 204/2000 ShieldRVs-PT-040A-LTLFireability-14 24497118 m, 215926 m/sec, 66544193 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 389 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 125/256 212/2000 ShieldRVs-PT-040A-LTLFireability-14 25492826 m, 199141 m/sec, 69345287 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 394 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 130/256 220/2000 ShieldRVs-PT-040A-LTLFireability-14 26452816 m, 191998 m/sec, 72118665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 399 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 135/256 228/2000 ShieldRVs-PT-040A-LTLFireability-14 27372515 m, 183939 m/sec, 74872635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 404 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 140/256 236/2000 ShieldRVs-PT-040A-LTLFireability-14 28286884 m, 182873 m/sec, 77629446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 409 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 145/256 243/2000 ShieldRVs-PT-040A-LTLFireability-14 29177242 m, 178071 m/sec, 80345884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 414 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 150/256 250/2000 ShieldRVs-PT-040A-LTLFireability-14 30073306 m, 179212 m/sec, 83103241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 419 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 155/256 259/2000 ShieldRVs-PT-040A-LTLFireability-14 31085748 m, 202488 m/sec, 85901540 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 424 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 160/256 267/2000 ShieldRVs-PT-040A-LTLFireability-14 32115601 m, 205970 m/sec, 88714363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 429 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 165/256 276/2000 ShieldRVs-PT-040A-LTLFireability-14 33109969 m, 198873 m/sec, 91502208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 434 secs. Pages in use: 276
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 170/256 284/2000 ShieldRVs-PT-040A-LTLFireability-14 34087200 m, 195446 m/sec, 94293284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 439 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 175/256 292/2000 ShieldRVs-PT-040A-LTLFireability-14 35037155 m, 189991 m/sec, 97052315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 444 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 180/256 299/2000 ShieldRVs-PT-040A-LTLFireability-14 35972819 m, 187132 m/sec, 99805447 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 449 secs. Pages in use: 299
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 185/256 307/2000 ShieldRVs-PT-040A-LTLFireability-14 36890154 m, 183467 m/sec, 102531698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 454 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 190/256 315/2000 ShieldRVs-PT-040A-LTLFireability-14 37827559 m, 187481 m/sec, 105283457 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 459 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 195/256 322/2000 ShieldRVs-PT-040A-LTLFireability-14 38737972 m, 182082 m/sec, 108010203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 464 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 200/256 331/2000 ShieldRVs-PT-040A-LTLFireability-14 39785035 m, 209412 m/sec, 110795633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 469 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 205/256 340/2000 ShieldRVs-PT-040A-LTLFireability-14 40788079 m, 200608 m/sec, 113563691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 474 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 210/256 348/2000 ShieldRVs-PT-040A-LTLFireability-14 41791344 m, 200653 m/sec, 116339939 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 479 secs. Pages in use: 348
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 215/256 356/2000 ShieldRVs-PT-040A-LTLFireability-14 42816313 m, 204993 m/sec, 119083658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 484 secs. Pages in use: 356
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 220/256 365/2000 ShieldRVs-PT-040A-LTLFireability-14 43797538 m, 196245 m/sec, 121838526 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 489 secs. Pages in use: 365
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 225/256 372/2000 ShieldRVs-PT-040A-LTLFireability-14 44740149 m, 188522 m/sec, 124620877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 494 secs. Pages in use: 372
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 230/256 380/2000 ShieldRVs-PT-040A-LTLFireability-14 45701308 m, 192231 m/sec, 127364327 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 499 secs. Pages in use: 380
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 235/256 388/2000 ShieldRVs-PT-040A-LTLFireability-14 46631054 m, 185949 m/sec, 130071044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 504 secs. Pages in use: 388
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 240/256 396/2000 ShieldRVs-PT-040A-LTLFireability-14 47582341 m, 190257 m/sec, 132773767 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 509 secs. Pages in use: 396
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 245/256 404/2000 ShieldRVs-PT-040A-LTLFireability-14 48507660 m, 185063 m/sec, 135471228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 514 secs. Pages in use: 404
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 250/256 413/2000 ShieldRVs-PT-040A-LTLFireability-14 49622888 m, 223045 m/sec, 138282326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 519 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 LTL EXCL 255/256 422/2000 ShieldRVs-PT-040A-LTLFireability-14 50771514 m, 229725 m/sec, 141132951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 524 secs. Pages in use: 422
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 51 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-14 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 529 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 ShieldRVs-PT-040A-LTLFireability-13
[[35mlola[0m][I] time limit : 255 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 ShieldRVs-PT-040A-LTLFireability-14
[[35mlola[0m][I] time limit : 3071 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3454
[[35mlola[0m][I] fired transitions : 3454
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 51 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-14 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 534 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 ShieldRVs-PT-040A-LTLFireability-10
[[35mlola[0m][I] time limit : 278 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3455
[[35mlola[0m][I] fired transitions : 3456
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 ShieldRVs-PT-040A-LTLFireability-07
[[35mlola[0m][I] time limit : 306 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3490
[[35mlola[0m][I] fired transitions : 3490
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 ShieldRVs-PT-040A-LTLFireability-06
[[35mlola[0m][I] time limit : 340 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 27 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 19 ShieldRVs-PT-040A-LTLFireability-05
[[35mlola[0m][I] time limit : 383 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 24 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3454
[[35mlola[0m][I] fired transitions : 3454
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 ShieldRVs-PT-040A-LTLFireability-04
[[35mlola[0m][I] time limit : 511 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 5/511 5/2000 ShieldRVs-PT-040A-LTLFireability-04 455336 m, 91067 m/sec, 3521351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 539 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 10/511 8/2000 ShieldRVs-PT-040A-LTLFireability-04 857769 m, 80486 m/sec, 7075546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 544 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 15/511 12/2000 ShieldRVs-PT-040A-LTLFireability-04 1244606 m, 77367 m/sec, 10614990 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 549 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 20/511 15/2000 ShieldRVs-PT-040A-LTLFireability-04 1615608 m, 74200 m/sec, 14138909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 554 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 25/511 18/2000 ShieldRVs-PT-040A-LTLFireability-04 1965922 m, 70062 m/sec, 17652258 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 559 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 30/511 21/2000 ShieldRVs-PT-040A-LTLFireability-04 2336534 m, 74122 m/sec, 21155162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 564 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 35/511 25/2000 ShieldRVs-PT-040A-LTLFireability-04 2705290 m, 73751 m/sec, 24642489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 569 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 40/511 28/2000 ShieldRVs-PT-040A-LTLFireability-04 3042198 m, 67381 m/sec, 28100868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 574 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 45/511 31/2000 ShieldRVs-PT-040A-LTLFireability-04 3388974 m, 69355 m/sec, 31559122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 579 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 50/511 34/2000 ShieldRVs-PT-040A-LTLFireability-04 3716296 m, 65464 m/sec, 35004805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 584 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 55/511 36/2000 ShieldRVs-PT-040A-LTLFireability-04 4024808 m, 61702 m/sec, 38436991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 589 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 60/511 39/2000 ShieldRVs-PT-040A-LTLFireability-04 4378738 m, 70786 m/sec, 41886227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 594 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 65/511 43/2000 ShieldRVs-PT-040A-LTLFireability-04 4744607 m, 73173 m/sec, 45352639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 599 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 70/511 46/2000 ShieldRVs-PT-040A-LTLFireability-04 5085186 m, 68115 m/sec, 48809637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 604 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 75/511 49/2000 ShieldRVs-PT-040A-LTLFireability-04 5426925 m, 68347 m/sec, 52269886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 609 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 80/511 52/2000 ShieldRVs-PT-040A-LTLFireability-04 5757656 m, 66146 m/sec, 55725161 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 614 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 85/511 54/2000 ShieldRVs-PT-040A-LTLFireability-04 6069153 m, 62299 m/sec, 59164795 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 619 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 90/511 57/2000 ShieldRVs-PT-040A-LTLFireability-04 6397479 m, 65665 m/sec, 62613579 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 624 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 95/511 60/2000 ShieldRVs-PT-040A-LTLFireability-04 6724268 m, 65357 m/sec, 66082895 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 629 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 100/511 63/2000 ShieldRVs-PT-040A-LTLFireability-04 7050631 m, 65272 m/sec, 69566422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 634 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 105/511 66/2000 ShieldRVs-PT-040A-LTLFireability-04 7358716 m, 61617 m/sec, 73033834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 639 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 110/511 69/2000 ShieldRVs-PT-040A-LTLFireability-04 7669271 m, 62111 m/sec, 76508400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 644 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 115/511 71/2000 ShieldRVs-PT-040A-LTLFireability-04 7964456 m, 59037 m/sec, 79966185 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 649 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 120/511 74/2000 ShieldRVs-PT-040A-LTLFireability-04 8237509 m, 54610 m/sec, 83390665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 654 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 125/511 77/2000 ShieldRVs-PT-040A-LTLFireability-04 8619967 m, 76491 m/sec, 86881487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 659 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 130/511 80/2000 ShieldRVs-PT-040A-LTLFireability-04 8978895 m, 71785 m/sec, 90364243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 664 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 135/511 83/2000 ShieldRVs-PT-040A-LTLFireability-04 9303250 m, 64871 m/sec, 93810049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 669 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 140/511 86/2000 ShieldRVs-PT-040A-LTLFireability-04 9660158 m, 71381 m/sec, 97278987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 674 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 145/511 89/2000 ShieldRVs-PT-040A-LTLFireability-04 9984148 m, 64798 m/sec, 100729528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 679 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 150/511 92/2000 ShieldRVs-PT-040A-LTLFireability-04 10284953 m, 60161 m/sec, 104163954 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 684 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 155/511 95/2000 ShieldRVs-PT-040A-LTLFireability-04 10628864 m, 68782 m/sec, 107622662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 689 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 160/511 98/2000 ShieldRVs-PT-040A-LTLFireability-04 10955193 m, 65265 m/sec, 111071666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 694 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 165/511 101/2000 ShieldRVs-PT-040A-LTLFireability-04 11262750 m, 61511 m/sec, 114503051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 699 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 170/511 103/2000 ShieldRVs-PT-040A-LTLFireability-04 11574015 m, 62253 m/sec, 117940336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 704 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 175/511 106/2000 ShieldRVs-PT-040A-LTLFireability-04 11868395 m, 58876 m/sec, 121357187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 709 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 180/511 109/2000 ShieldRVs-PT-040A-LTLFireability-04 12159532 m, 58227 m/sec, 124758871 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 714 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 185/511 111/2000 ShieldRVs-PT-040A-LTLFireability-04 12438059 m, 55705 m/sec, 128139382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 719 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 190/511 114/2000 ShieldRVs-PT-040A-LTLFireability-04 12784955 m, 69379 m/sec, 131611858 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 724 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 195/511 117/2000 ShieldRVs-PT-040A-LTLFireability-04 13109177 m, 64844 m/sec, 135063582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 729 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 200/511 120/2000 ShieldRVs-PT-040A-LTLFireability-04 13407224 m, 59609 m/sec, 138498002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 734 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 205/511 122/2000 ShieldRVs-PT-040A-LTLFireability-04 13727769 m, 64109 m/sec, 141957562 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 739 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 210/511 125/2000 ShieldRVs-PT-040A-LTLFireability-04 14024925 m, 59431 m/sec, 145398377 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 744 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 215/511 128/2000 ShieldRVs-PT-040A-LTLFireability-04 14310401 m, 57095 m/sec, 148827228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 749 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 220/511 130/2000 ShieldRVs-PT-040A-LTLFireability-04 14603115 m, 58542 m/sec, 152252233 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 754 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 225/511 133/2000 ShieldRVs-PT-040A-LTLFireability-04 14906849 m, 60746 m/sec, 155679153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 759 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 230/511 136/2000 ShieldRVs-PT-040A-LTLFireability-04 15198690 m, 58368 m/sec, 159097226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 764 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 235/511 138/2000 ShieldRVs-PT-040A-LTLFireability-04 15469651 m, 54192 m/sec, 162501641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 769 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 240/511 141/2000 ShieldRVs-PT-040A-LTLFireability-04 15759599 m, 57989 m/sec, 165936285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 774 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 245/511 143/2000 ShieldRVs-PT-040A-LTLFireability-04 16031660 m, 54412 m/sec, 169355084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 779 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 250/511 145/2000 ShieldRVs-PT-040A-LTLFireability-04 16299090 m, 53486 m/sec, 172762645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 784 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 255/511 148/2000 ShieldRVs-PT-040A-LTLFireability-04 16559271 m, 52036 m/sec, 176147081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 789 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 260/511 151/2000 ShieldRVs-PT-040A-LTLFireability-04 16948091 m, 77764 m/sec, 179641216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 794 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 265/511 154/2000 ShieldRVs-PT-040A-LTLFireability-04 17300029 m, 70387 m/sec, 183120984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 799 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 270/511 157/2000 ShieldRVs-PT-040A-LTLFireability-04 17642475 m, 68489 m/sec, 186600216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 804 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 275/511 160/2000 ShieldRVs-PT-040A-LTLFireability-04 17982724 m, 68049 m/sec, 190049447 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 809 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 280/511 163/2000 ShieldRVs-PT-040A-LTLFireability-04 18299821 m, 63419 m/sec, 193462796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 814 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 285/511 166/2000 ShieldRVs-PT-040A-LTLFireability-04 18592349 m, 58505 m/sec, 196877657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 819 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 290/511 169/2000 ShieldRVs-PT-040A-LTLFireability-04 18945278 m, 70585 m/sec, 200306387 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 824 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 295/511 172/2000 ShieldRVs-PT-040A-LTLFireability-04 19265822 m, 64108 m/sec, 203717438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 829 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 300/511 174/2000 ShieldRVs-PT-040A-LTLFireability-04 19564601 m, 59755 m/sec, 207113593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 834 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 305/511 177/2000 ShieldRVs-PT-040A-LTLFireability-04 19873569 m, 61793 m/sec, 210512886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 839 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 310/511 180/2000 ShieldRVs-PT-040A-LTLFireability-04 20167988 m, 58883 m/sec, 213905941 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 844 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 315/511 182/2000 ShieldRVs-PT-040A-LTLFireability-04 20455224 m, 57447 m/sec, 217290544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 849 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 320/511 185/2000 ShieldRVs-PT-040A-LTLFireability-04 20745255 m, 58006 m/sec, 220672248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 854 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 325/511 188/2000 ShieldRVs-PT-040A-LTLFireability-04 21083582 m, 67665 m/sec, 224108011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 859 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 330/511 191/2000 ShieldRVs-PT-040A-LTLFireability-04 21401395 m, 63562 m/sec, 227530316 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 864 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 335/511 193/2000 ShieldRVs-PT-040A-LTLFireability-04 21693382 m, 58397 m/sec, 230929005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 869 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 340/511 196/2000 ShieldRVs-PT-040A-LTLFireability-04 22013525 m, 64028 m/sec, 234352457 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 874 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 345/511 199/2000 ShieldRVs-PT-040A-LTLFireability-04 22306452 m, 58585 m/sec, 237751966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 879 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 350/511 201/2000 ShieldRVs-PT-040A-LTLFireability-04 22585209 m, 55751 m/sec, 241135104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 884 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 355/511 204/2000 ShieldRVs-PT-040A-LTLFireability-04 22879668 m, 58891 m/sec, 244531473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 889 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 360/511 207/2000 ShieldRVs-PT-040A-LTLFireability-04 23178823 m, 59831 m/sec, 247932943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 894 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 365/511 209/2000 ShieldRVs-PT-040A-LTLFireability-04 23468559 m, 57947 m/sec, 251331426 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 899 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 370/511 211/2000 ShieldRVs-PT-040A-LTLFireability-04 23736537 m, 53595 m/sec, 254710435 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 904 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 375/511 214/2000 ShieldRVs-PT-040A-LTLFireability-04 24025668 m, 57826 m/sec, 258109949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 909 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 380/511 216/2000 ShieldRVs-PT-040A-LTLFireability-04 24293477 m, 53561 m/sec, 261483018 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 914 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 385/511 219/2000 ShieldRVs-PT-040A-LTLFireability-04 24557128 m, 52730 m/sec, 264847789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 919 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 390/511 221/2000 ShieldRVs-PT-040A-LTLFireability-04 24809676 m, 50509 m/sec, 268193219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 924 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 395/511 224/2000 ShieldRVs-PT-040A-LTLFireability-04 25157841 m, 69633 m/sec, 271635242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 929 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 400/511 227/2000 ShieldRVs-PT-040A-LTLFireability-04 25479330 m, 64297 m/sec, 275059145 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 934 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 405/511 230/2000 ShieldRVs-PT-040A-LTLFireability-04 25776370 m, 59408 m/sec, 278462615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 939 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 410/511 232/2000 ShieldRVs-PT-040A-LTLFireability-04 26089632 m, 62652 m/sec, 281882410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 944 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 415/511 235/2000 ShieldRVs-PT-040A-LTLFireability-04 26384701 m, 59013 m/sec, 285283607 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 949 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 420/511 238/2000 ShieldRVs-PT-040A-LTLFireability-04 26666761 m, 56412 m/sec, 288634766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 954 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 425/511 240/2000 ShieldRVs-PT-040A-LTLFireability-04 26944177 m, 55483 m/sec, 291950854 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 959 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 430/511 243/2000 ShieldRVs-PT-040A-LTLFireability-04 27243373 m, 59839 m/sec, 295279782 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 964 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 435/511 245/2000 ShieldRVs-PT-040A-LTLFireability-04 27531157 m, 57556 m/sec, 298623956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 969 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 440/511 248/2000 ShieldRVs-PT-040A-LTLFireability-04 27800431 m, 53854 m/sec, 301943724 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 974 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 445/511 250/2000 ShieldRVs-PT-040A-LTLFireability-04 28076066 m, 55127 m/sec, 305248409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 979 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 450/511 252/2000 ShieldRVs-PT-040A-LTLFireability-04 28342140 m, 53214 m/sec, 308550567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 984 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 455/511 255/2000 ShieldRVs-PT-040A-LTLFireability-04 28606208 m, 52813 m/sec, 311896147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 989 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 460/511 257/2000 ShieldRVs-PT-040A-LTLFireability-04 28853071 m, 49372 m/sec, 315213094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 994 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 465/511 260/2000 ShieldRVs-PT-040A-LTLFireability-04 29158424 m, 61070 m/sec, 318684806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 999 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 470/511 262/2000 ShieldRVs-PT-040A-LTLFireability-04 29455178 m, 59350 m/sec, 322110367 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1004 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 475/511 265/2000 ShieldRVs-PT-040A-LTLFireability-04 29742960 m, 57556 m/sec, 325499074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1009 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 480/511 267/2000 ShieldRVs-PT-040A-LTLFireability-04 30016529 m, 54713 m/sec, 328879775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1014 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 485/511 270/2000 ShieldRVs-PT-040A-LTLFireability-04 30301087 m, 56911 m/sec, 332286830 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1019 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 490/511 272/2000 ShieldRVs-PT-040A-LTLFireability-04 30568540 m, 53490 m/sec, 335668188 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1024 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 495/511 274/2000 ShieldRVs-PT-040A-LTLFireability-04 30826058 m, 51503 m/sec, 339033106 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1029 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 500/511 277/2000 ShieldRVs-PT-040A-LTLFireability-04 31089752 m, 52738 m/sec, 342411979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1034 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 505/511 279/2000 ShieldRVs-PT-040A-LTLFireability-04 31369677 m, 55985 m/sec, 345813360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1039 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 510/511 282/2000 ShieldRVs-PT-040A-LTLFireability-04 31638185 m, 53701 m/sec, 349204785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1044 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 17 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-04 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1049 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 ShieldRVs-PT-040A-LTLFireability-02
[[35mlola[0m][I] time limit : 510 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 ShieldRVs-PT-040A-LTLFireability-04
[[35mlola[0m][I] time limit : 2551 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 5/510 4/2000 ShieldRVs-PT-040A-LTLFireability-02 449230 m, 89846 m/sec, 3524290 t fired, .
[[35mlola[0m][.] 17 LTL EXCL 5/2551 5/5 ShieldRVs-PT-040A-LTLFireability-04 454111 m, -6236814 m/sec, 3509786 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1054 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 17 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-04 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 10/510 8/2000 ShieldRVs-PT-040A-LTLFireability-02 849224 m, 79998 m/sec, 7054877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1059 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 15/510 11/2000 ShieldRVs-PT-040A-LTLFireability-02 1236309 m, 77417 m/sec, 10597038 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1064 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 20/510 15/2000 ShieldRVs-PT-040A-LTLFireability-02 1608409 m, 74420 m/sec, 14131619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1069 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 25/510 18/2000 ShieldRVs-PT-040A-LTLFireability-02 1959742 m, 70266 m/sec, 17655071 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1074 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 30/510 21/2000 ShieldRVs-PT-040A-LTLFireability-02 2332677 m, 74587 m/sec, 21171578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1079 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 35/510 25/2000 ShieldRVs-PT-040A-LTLFireability-02 2703149 m, 74094 m/sec, 24685636 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1084 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 40/510 28/2000 ShieldRVs-PT-040A-LTLFireability-02 3044283 m, 68226 m/sec, 28190339 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1089 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 45/510 31/2000 ShieldRVs-PT-040A-LTLFireability-02 3396918 m, 70527 m/sec, 31697328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1094 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 50/510 34/2000 ShieldRVs-PT-040A-LTLFireability-02 3728426 m, 66301 m/sec, 35205712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1099 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 55/510 36/2000 ShieldRVs-PT-040A-LTLFireability-02 4039676 m, 62250 m/sec, 38683815 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1104 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 60/510 40/2000 ShieldRVs-PT-040A-LTLFireability-02 4404080 m, 72880 m/sec, 42181899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1109 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 65/510 43/2000 ShieldRVs-PT-040A-LTLFireability-02 4772504 m, 73684 m/sec, 45693796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1114 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 70/510 46/2000 ShieldRVs-PT-040A-LTLFireability-02 5113093 m, 68117 m/sec, 49193142 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1119 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 75/510 49/2000 ShieldRVs-PT-040A-LTLFireability-02 5466126 m, 70606 m/sec, 52699295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1124 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 80/510 52/2000 ShieldRVs-PT-040A-LTLFireability-02 5795322 m, 65839 m/sec, 56188183 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1129 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 85/510 55/2000 ShieldRVs-PT-040A-LTLFireability-02 6106482 m, 62232 m/sec, 59665951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1134 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 90/510 58/2000 ShieldRVs-PT-040A-LTLFireability-02 6442911 m, 67285 m/sec, 63151191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1139 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 95/510 61/2000 ShieldRVs-PT-040A-LTLFireability-02 6775581 m, 66534 m/sec, 66643077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1144 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 100/510 64/2000 ShieldRVs-PT-040A-LTLFireability-02 7091941 m, 63272 m/sec, 70124464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1149 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 105/510 66/2000 ShieldRVs-PT-040A-LTLFireability-02 7398434 m, 61298 m/sec, 73517749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1154 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 110/510 69/2000 ShieldRVs-PT-040A-LTLFireability-02 7700337 m, 60380 m/sec, 76966070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1159 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 115/510 72/2000 ShieldRVs-PT-040A-LTLFireability-02 7993843 m, 58701 m/sec, 80426930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1164 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 120/510 74/2000 ShieldRVs-PT-040A-LTLFireability-02 8264450 m, 54121 m/sec, 83841414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1169 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 125/510 77/2000 ShieldRVs-PT-040A-LTLFireability-02 8661269 m, 79363 m/sec, 87345202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1174 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 130/510 81/2000 ShieldRVs-PT-040A-LTLFireability-02 9016660 m, 71078 m/sec, 90817998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1179 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 135/510 84/2000 ShieldRVs-PT-040A-LTLFireability-02 9350704 m, 66808 m/sec, 94268919 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1184 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 140/510 87/2000 ShieldRVs-PT-040A-LTLFireability-02 9695545 m, 68968 m/sec, 97728868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1189 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 145/510 90/2000 ShieldRVs-PT-040A-LTLFireability-02 10017449 m, 64380 m/sec, 101171543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1194 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 150/510 92/2000 ShieldRVs-PT-040A-LTLFireability-02 10312367 m, 58983 m/sec, 104594512 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1199 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 155/510 95/2000 ShieldRVs-PT-040A-LTLFireability-02 10666669 m, 70860 m/sec, 108069525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1204 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 160/510 98/2000 ShieldRVs-PT-040A-LTLFireability-02 10990952 m, 64856 m/sec, 111522853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1209 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 165/510 101/2000 ShieldRVs-PT-040A-LTLFireability-02 11294615 m, 60732 m/sec, 114969666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1214 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 170/510 104/2000 ShieldRVs-PT-040A-LTLFireability-02 11608063 m, 62689 m/sec, 118418273 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1219 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 175/510 106/2000 ShieldRVs-PT-040A-LTLFireability-02 11905696 m, 59526 m/sec, 121849206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1224 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 180/510 109/2000 ShieldRVs-PT-040A-LTLFireability-02 12195194 m, 57899 m/sec, 125267443 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1229 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 185/510 112/2000 ShieldRVs-PT-040A-LTLFireability-02 12490436 m, 59048 m/sec, 128683229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1234 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 190/510 115/2000 ShieldRVs-PT-040A-LTLFireability-02 12830977 m, 68108 m/sec, 132157210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1239 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 195/510 117/2000 ShieldRVs-PT-040A-LTLFireability-02 13151525 m, 64109 m/sec, 135622195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1244 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 200/510 120/2000 ShieldRVs-PT-040A-LTLFireability-02 13453268 m, 60348 m/sec, 139073997 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1249 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 205/510 123/2000 ShieldRVs-PT-040A-LTLFireability-02 13773137 m, 63973 m/sec, 142538461 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1254 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 210/510 126/2000 ShieldRVs-PT-040A-LTLFireability-02 14066506 m, 58673 m/sec, 145974181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1259 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 215/510 128/2000 ShieldRVs-PT-040A-LTLFireability-02 14349266 m, 56552 m/sec, 149403401 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1264 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 220/510 131/2000 ShieldRVs-PT-040A-LTLFireability-02 14649761 m, 60099 m/sec, 152831809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1269 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 225/510 133/2000 ShieldRVs-PT-040A-LTLFireability-02 14946959 m, 59439 m/sec, 156254663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1274 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 230/510 136/2000 ShieldRVs-PT-040A-LTLFireability-02 15238437 m, 58295 m/sec, 159680112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1279 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 235/510 138/2000 ShieldRVs-PT-040A-LTLFireability-02 15511069 m, 54526 m/sec, 163084386 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1284 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 240/510 141/2000 ShieldRVs-PT-040A-LTLFireability-02 15803410 m, 58468 m/sec, 166524635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1289 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 245/510 143/2000 ShieldRVs-PT-040A-LTLFireability-02 16074113 m, 54140 m/sec, 169942457 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1294 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 250/510 146/2000 ShieldRVs-PT-040A-LTLFireability-02 16337417 m, 52660 m/sec, 173345961 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1299 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 255/510 148/2000 ShieldRVs-PT-040A-LTLFireability-02 16627271 m, 57970 m/sec, 176755634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1304 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 260/510 152/2000 ShieldRVs-PT-040A-LTLFireability-02 17001288 m, 74803 m/sec, 180248712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1309 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 265/510 155/2000 ShieldRVs-PT-040A-LTLFireability-02 17357245 m, 71191 m/sec, 183735509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1314 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 270/510 158/2000 ShieldRVs-PT-040A-LTLFireability-02 17699071 m, 68365 m/sec, 187208511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1319 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 275/510 161/2000 ShieldRVs-PT-040A-LTLFireability-02 18032193 m, 66624 m/sec, 190676389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1324 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 280/510 164/2000 ShieldRVs-PT-040A-LTLFireability-02 18353490 m, 64259 m/sec, 194132991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1329 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 285/510 166/2000 ShieldRVs-PT-040A-LTLFireability-02 18666055 m, 62513 m/sec, 197573373 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1334 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 290/510 169/2000 ShieldRVs-PT-040A-LTLFireability-02 19007952 m, 68379 m/sec, 201037941 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1339 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 295/510 172/2000 ShieldRVs-PT-040A-LTLFireability-02 19327111 m, 63831 m/sec, 204473683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1344 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 300/510 175/2000 ShieldRVs-PT-040A-LTLFireability-02 19617053 m, 57988 m/sec, 207862949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1349 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 305/510 178/2000 ShieldRVs-PT-040A-LTLFireability-02 19941235 m, 64836 m/sec, 211317809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1354 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 310/510 180/2000 ShieldRVs-PT-040A-LTLFireability-02 20236225 m, 58998 m/sec, 214742106 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1359 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 315/510 183/2000 ShieldRVs-PT-040A-LTLFireability-02 20516841 m, 56123 m/sec, 218154470 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1364 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 320/510 186/2000 ShieldRVs-PT-040A-LTLFireability-02 20833372 m, 63306 m/sec, 221593583 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1369 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 325/510 189/2000 ShieldRVs-PT-040A-LTLFireability-02 21159134 m, 65152 m/sec, 225054086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1374 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 330/510 191/2000 ShieldRVs-PT-040A-LTLFireability-02 21482652 m, 64703 m/sec, 228505763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1379 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 335/510 194/2000 ShieldRVs-PT-040A-LTLFireability-02 21788339 m, 61137 m/sec, 231942314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1384 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 340/510 197/2000 ShieldRVs-PT-040A-LTLFireability-02 22098041 m, 61940 m/sec, 235403662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1389 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 345/510 199/2000 ShieldRVs-PT-040A-LTLFireability-02 22389482 m, 58288 m/sec, 238816957 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1394 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 350/510 202/2000 ShieldRVs-PT-040A-LTLFireability-02 22662980 m, 54699 m/sec, 242211538 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1399 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 355/510 205/2000 ShieldRVs-PT-040A-LTLFireability-02 22969742 m, 61352 m/sec, 245641344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1404 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 360/510 207/2000 ShieldRVs-PT-040A-LTLFireability-02 23269725 m, 59996 m/sec, 249074235 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1409 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 365/510 210/2000 ShieldRVs-PT-040A-LTLFireability-02 23559824 m, 58019 m/sec, 252512014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1414 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 370/510 212/2000 ShieldRVs-PT-040A-LTLFireability-02 23838390 m, 55713 m/sec, 255936365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1419 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 375/510 215/2000 ShieldRVs-PT-040A-LTLFireability-02 24121768 m, 56675 m/sec, 259362739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1424 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 380/510 217/2000 ShieldRVs-PT-040A-LTLFireability-02 24389385 m, 53523 m/sec, 262762398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1429 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 385/510 220/2000 ShieldRVs-PT-040A-LTLFireability-02 24647092 m, 51541 m/sec, 266151328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1434 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 390/510 222/2000 ShieldRVs-PT-040A-LTLFireability-02 24950221 m, 60625 m/sec, 269573864 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1439 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 395/510 225/2000 ShieldRVs-PT-040A-LTLFireability-02 25277990 m, 65553 m/sec, 273033919 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1444 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 400/510 228/2000 ShieldRVs-PT-040A-LTLFireability-02 25601793 m, 64760 m/sec, 276497305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1449 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 405/510 231/2000 ShieldRVs-PT-040A-LTLFireability-02 25907319 m, 61105 m/sec, 279942843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1454 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 410/510 234/2000 ShieldRVs-PT-040A-LTLFireability-02 26218062 m, 62148 m/sec, 283401862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1459 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 415/510 236/2000 ShieldRVs-PT-040A-LTLFireability-02 26512076 m, 58802 m/sec, 286837768 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1464 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 420/510 239/2000 ShieldRVs-PT-040A-LTLFireability-02 26786860 m, 54956 m/sec, 290249171 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1469 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 425/510 241/2000 ShieldRVs-PT-040A-LTLFireability-02 27093267 m, 61281 m/sec, 293673862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1474 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 430/510 244/2000 ShieldRVs-PT-040A-LTLFireability-02 27390672 m, 59481 m/sec, 297096758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1479 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 435/510 247/2000 ShieldRVs-PT-040A-LTLFireability-02 27680455 m, 57956 m/sec, 300523613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1484 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 440/510 249/2000 ShieldRVs-PT-040A-LTLFireability-02 27957865 m, 55482 m/sec, 303930660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1489 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 445/510 252/2000 ShieldRVs-PT-040A-LTLFireability-02 28241541 m, 56735 m/sec, 307347424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1494 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 450/510 254/2000 ShieldRVs-PT-040A-LTLFireability-02 28509399 m, 53571 m/sec, 310742329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1499 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 455/510 256/2000 ShieldRVs-PT-040A-LTLFireability-02 28767352 m, 51590 m/sec, 314125844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1504 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 460/510 259/2000 ShieldRVs-PT-040A-LTLFireability-02 29048281 m, 56185 m/sec, 317527399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1509 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 465/510 261/2000 ShieldRVs-PT-040A-LTLFireability-02 29351170 m, 60577 m/sec, 320947855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1514 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 470/510 264/2000 ShieldRVs-PT-040A-LTLFireability-02 29642205 m, 58207 m/sec, 324355805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1519 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 475/510 266/2000 ShieldRVs-PT-040A-LTLFireability-02 29911885 m, 53936 m/sec, 327741911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1524 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 480/510 269/2000 ShieldRVs-PT-040A-LTLFireability-02 30199257 m, 57474 m/sec, 331154032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1529 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 485/510 271/2000 ShieldRVs-PT-040A-LTLFireability-02 30469332 m, 54015 m/sec, 334550298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1534 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 490/510 274/2000 ShieldRVs-PT-040A-LTLFireability-02 30736565 m, 53446 m/sec, 337942330 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1539 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 495/510 276/2000 ShieldRVs-PT-040A-LTLFireability-02 30984546 m, 49596 m/sec, 341311302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1544 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 500/510 278/2000 ShieldRVs-PT-040A-LTLFireability-02 31277274 m, 58545 m/sec, 344736709 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1549 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 505/510 281/2000 ShieldRVs-PT-040A-LTLFireability-02 31546201 m, 53785 m/sec, 348137262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1554 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 510/510 283/2000 ShieldRVs-PT-040A-LTLFireability-02 31810334 m, 52826 m/sec, 351544051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1559 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 11 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1564 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 7 ShieldRVs-PT-040A-LTLFireability-01
[[35mlola[0m][I] time limit : 509 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 ShieldRVs-PT-040A-LTLFireability-02
[[35mlola[0m][I] time limit : 2036 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 5/509 5/5 ShieldRVs-PT-040A-LTLFireability-02 460897 m, -6269887 m/sec, 3630956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1569 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 11 (type EXCL) for ShieldRVs-PT-040A-LTLFireability-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1574 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 ShieldRVs-PT-040A-LTLFireability-09
[[35mlola[0m][I] time limit : 675 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 5/675 7/2000 ShieldRVs-PT-040A-LTLFireability-09 785778 m, 157155 m/sec, 2076244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1579 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 10/675 14/2000 ShieldRVs-PT-040A-LTLFireability-09 1599155 m, 162675 m/sec, 4233434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1584 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 15/675 21/2000 ShieldRVs-PT-040A-LTLFireability-09 2340250 m, 148219 m/sec, 6354238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1589 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 20/675 27/2000 ShieldRVs-PT-040A-LTLFireability-09 3083640 m, 148678 m/sec, 8471542 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1594 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 25/675 33/2000 ShieldRVs-PT-040A-LTLFireability-09 3826227 m, 148517 m/sec, 10553583 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1599 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 30/675 39/2000 ShieldRVs-PT-040A-LTLFireability-09 4500933 m, 134941 m/sec, 12669116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1604 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-040A-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-040A-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ShieldRVs-PT-040A-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 35/675 42/2000 ShieldRVs-PT-040A-LTLFireability-09 4873259 m, 74465 m/sec, 13889516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1609 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ShieldRVs-PT-040A"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ShieldRVs-PT-040A, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r357-tall-171683764300836"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ShieldRVs-PT-040A.tgz
mv ShieldRVs-PT-040A execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;