About the Execution of LoLA for ShieldRVs-PT-003A
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 493.739 | 19062.00 | 19664.00 | 75.30 | TTFTTTTTTFFTFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r357-tall-171683764100738.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ShieldRVs-PT-003A, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r357-tall-171683764100738
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 432K
-rw-r--r-- 1 mcc users 7.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Apr 23 07:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 23 07:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.3K Apr 12 17:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 98K Apr 12 17:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Apr 12 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Apr 12 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 07:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 19K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-00
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-01
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-02
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-03
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-04
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-05
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-06
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-07
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-08
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-09
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-10
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2024-11
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2023-12
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2023-13
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2023-14
FORMULA_NAME ShieldRVs-PT-003A-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717168720209
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2023-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldRVs-PT-003A-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-01: CONJ true CONJ[0m
[[35mlola[0m] [1m[31mShieldRVs-PT-003A-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-06: EXEG true state space /EXEG[0m
[[35mlola[0m] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-08: DISJ true state space / EG[0m
[[35mlola[0m] [1m[31mShieldRVs-PT-003A-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mShieldRVs-PT-003A-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mShieldRVs-PT-003A-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mShieldRVs-PT-003A-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mShieldRVs-PT-003A-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mShieldRVs-PT-003A-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 19 secs. Pages in use: 7
BK_STOP 1717168739271
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 ShieldRVs-PT-003A-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 45
[[35mlola[0m][I] fired transitions : 44
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 ShieldRVs-PT-003A-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 49
[[35mlola[0m][I] fired transitions : 49
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 ShieldRVs-PT-003A-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 22 ShieldRVs-PT-003A-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 28 ShieldRVs-PT-003A-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5417
[[35mlola[0m][I] fired transitions : 14677
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 56 (type EXCL) for 22 ShieldRVs-PT-003A-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 56 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 50
[[35mlola[0m][I] fired transitions : 49
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 60 (type EQUN) for ShieldRVs-PT-003A-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 ShieldRVs-PT-003A-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 49
[[35mlola[0m][I] fired transitions : 96
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 ShieldRVs-PT-003A-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 48
[[35mlola[0m][I] fired transitions : 47
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 ShieldRVs-PT-003A-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for ShieldRVs-PT-003A-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for ShieldRVs-PT-003A-CTLFireability-2024-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 102489
[[35mlola[0m][I] fired transitions : 262596
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 ShieldRVs-PT-003A-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-06: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-003A-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-003A-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-08: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 5/327 4/2000 ShieldRVs-PT-003A-CTLFireability-2024-09 970645 m, 194129 m/sec, 6907643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 8 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1530495
[[35mlola[0m][I] fired transitions : 10891967
[[35mlola[0m][I] time used : 8
[[35mlola[0m][I] memory pages used : 7
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 ShieldRVs-PT-003A-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 47
[[35mlola[0m][I] fired transitions : 46
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 3 ShieldRVs-PT-003A-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 398 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 6 (type EXCL) for 3 ShieldRVs-PT-003A-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 448 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-003A-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-06: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-003A-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-003A-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-003A-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-01: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-08: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 6 CTL EXCL 2/448 4/2000 ShieldRVs-PT-003A-CTLFireability-2024-01 737010 m, 147402 m/sec, 3862081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 13 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 6 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1429463
[[35mlola[0m][I] fired transitions : 7529407
[[35mlola[0m][I] time used : 4
[[35mlola[0m][I] memory pages used : 6
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 ShieldRVs-PT-003A-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 512 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5724
[[35mlola[0m][I] fired transitions : 21162
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 28 ShieldRVs-PT-003A-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 597 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 41
[[35mlola[0m][I] fired transitions : 41
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 ShieldRVs-PT-003A-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 896 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2023-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 45
[[35mlola[0m][I] fired transitions : 45
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 ShieldRVs-PT-003A-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 1195 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 46
[[35mlola[0m][I] fired transitions : 45
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 ShieldRVs-PT-003A-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 1792 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-01: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-003A-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-06: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-08: DISJ true state space / EG[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-003A-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-003A-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-003A-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldRVs-PT-003A-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mShieldRVs-PT-003A-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldRVs-PT-003A-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 3/1792 4/2000 ShieldRVs-PT-003A-CTLFireability-2023-15 920568 m, 184113 m/sec, 4931705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 18 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1093925
[[35mlola[0m][I] fired transitions : 5837921
[[35mlola[0m][I] time used : 4
[[35mlola[0m][I] memory pages used : 5
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 ShieldRVs-PT-003A-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 3581 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for ShieldRVs-PT-003A-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 111
[[35mlola[0m][I] fired transitions : 442
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ShieldRVs-PT-003A"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ShieldRVs-PT-003A, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r357-tall-171683764100738"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ShieldRVs-PT-003A.tgz
mv ShieldRVs-PT-003A execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;