About the Execution of LoLA for ShieldPPPs-PT-100A
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 0.000 | 2032306.00 | 0.00 | 0.00 | F??????FT??TTF?? | normal |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r357-tall-171683763500514.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ShieldPPPs-PT-100A, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r357-tall-171683763500514
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 7.7K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K May 19 07:16 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K May 19 16:35 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:32 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 19:11 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 13 13:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 150K Apr 13 13:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.5K Apr 13 13:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 60K Apr 13 13:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 907K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-00
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-01
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-02
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-03
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-04
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-05
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-06
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-07
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-08
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-09
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-10
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2024-11
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2023-12
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2023-13
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2023-14
FORMULA_NAME ShieldPPPs-PT-100A-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717145180131
FORMULA ShieldPPPs-PT-100A-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPs-PT-100A-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPs-PT-100A-CTLFireability-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPs-PT-100A-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPs-PT-100A-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ShieldPPPs-PT-100A-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717147212437
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 0 ShieldPPPs-PT-100A-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 202 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 53 (type FNDP) for 0 ShieldPPPs-PT-100A-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 0 ShieldPPPs-PT-100A-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for ShieldPPPs-PT-100A-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 226
[[35mlola[0m][I] fired transitions : 225
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 53 (type FNDP) for ShieldPPPs-PT-100A-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][W] CANCELED task # 54 (type EQUN) for ShieldPPPs-PT-100A-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][I] FINISHED task # 53 (type FNDP) for ShieldPPPs-PT-100A-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldPPPs-PT-100A-CTLFireability-2024-00: AG false state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 162 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 ShieldPPPs-PT-100A-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 214 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 9 ShieldPPPs-PT-100A-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldPPPs-PT-100A-CTLFireability-2024-00: AG false state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 4/214 3/2000 ShieldPPPs-PT-100A-CTLFireability-2023-15 153091 m, 30618 m/sec, 704193 t fired, .
[[35mlola[0m][.] 60 EF STEQ 4/3437 0/5 ShieldPPPs-PT-100A-CTLFireability-2024-03 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m[31mShieldPPPs-PT-100A-CTLFireability-2024-00: AG false state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 9/214 5/2000 ShieldPPPs-PT-100A-CTLFireability-2023-15 300200 m, 29421 m/sec, 1533910 t fired, .
[[35mlola[0m][.] 60 EF STEQ 9/3437 0/5 ShieldPPPs-PT-100A-CTLFireability-2024-03 sara not yet started (preprocessing).
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 14/214 8/2000 ShieldPPPs-PT-100A-CTLFireability-2023-15 438606 m, 27681 m/sec, 2357992 t fired, .
[[35mlola[0m][.] 60 EF STEQ 14/3437 0/5 ShieldPPPs-PT-100A-CTLFireability-2024-03 sara not yet started (preprocessing).
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[[35mlola[0m][.]
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for ShieldPPPs-PT-100A-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4244
[[35mlola[0m][I] fired transitions : 4246
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 ShieldPPPs-PT-100A-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 267 sec
[[35mlola[0m][I] memory limit: 2000 pages
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[[35mlola[0m][.] [1m[31mShieldPPPs-PT-100A-CTLFireability-2024-00: AG false state space[0m
[[35mlola[0m][.] [1m[32mShieldPPPs-PT-100A-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mShieldPPPs-PT-100A-CTLFireability-2023-12: CTL true CTL model checker[0m
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 35 CTL EXCL 5/267 5/2000 ShieldPPPs-PT-100A-CTLFireability-2024-10 302838 m, 60567 m/sec, 808196 t fired, .
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 35 CTL EXCL 10/267 9/2000 ShieldPPPs-PT-100A-CTLFireability-2024-10 571216 m, 53675 m/sec, 1615559 t fired, .
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 35 CTL EXCL 15/267 12/2000 ShieldPPPs-PT-100A-CTLFireability-2024-10 834516 m, 52660 m/sec, 2426343 t fired, .
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 35 CTL EXCL 20/267 15/2000 ShieldPPPs-PT-100A-CTLFireability-2024-10 1076704 m, 48437 m/sec, 3234127 t fired, .
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 35 CTL EXCL 25/267 19/2000 ShieldPPPs-PT-100A-CTLFireability-2024-10 1300130 m, 44685 m/sec, 4043082 t fired, .
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 35 CTL EXCL 30/267 22/2000 ShieldPPPs-PT-100A-CTLFireability-2024-10 1518888 m, 43751 m/sec, 4852234 t fired, .
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[[35mlola[0m][.] 35 CTL EXCL 35/267 25/2000 ShieldPPPs-PT-100A-CTLFireability-2024-10 1749259 m, 46074 m/sec, 5661097 t fired, .
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 35 CTL EXCL 255/267 157/2000 ShieldPPPs-PT-100A-CTLFireability-2024-10 11405716 m, 38927 m/sec, 41193849 t fired, .
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[[35mlola[0m][.] [1m[32mShieldPPPs-PT-100A-CTLFireability-2024-11: CTL true CTL model checker[0m
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 35 CTL EXCL 260/267 160/2000 ShieldPPPs-PT-100A-CTLFireability-2024-10 11595424 m, 37941 m/sec, 42014568 t fired, .
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[[35mlola[0m][.] [1m[32mShieldPPPs-PT-100A-CTLFireability-2024-11: CTL true CTL model checker[0m
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 35 CTL EXCL 265/267 163/2000 ShieldPPPs-PT-100A-CTLFireability-2024-10 11829839 m, 46883 m/sec, 42828965 t fired, .
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[[35mlola[0m][.] [1m[31mShieldPPPs-PT-100A-CTLFireability-2024-00: AG false state space[0m
[[35mlola[0m][.] [1m[32mShieldPPPs-PT-100A-CTLFireability-2024-11: CTL true CTL model checker[0m
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][I] markings : 5685
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mShieldPPPs-PT-100A-CTLFireability-2024-00: AG false state space[0m
[[35mlola[0m][.] [1m[32mShieldPPPs-PT-100A-CTLFireability-2024-08: CTL true CTL model checker[0m
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 35 CTL EXCL 5/267 5/5 ShieldPPPs-PT-100A-CTLFireability-2024-10 288780 m, -2308211 m/sec, 770027 t fired, .
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 17 CTL EXCL 5/325 4/2000 ShieldPPPs-PT-100A-CTLFireability-2024-04 211793 m, 42358 m/sec, 807855 t fired, .
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-05: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-06: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 17 CTL EXCL 10/325 7/2000 ShieldPPPs-PT-100A-CTLFireability-2024-04 381161 m, 33873 m/sec, 1618271 t fired, .
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[[35mlola[0m][.] ShieldPPPs-PT-100A-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 1 0
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[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 9 ShieldPPPs-PT-100A-CTLFireability-2024-03
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 404 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ShieldPPPs-PT-100A"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ShieldPPPs-PT-100A, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r357-tall-171683763500514"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ShieldPPPs-PT-100A.tgz
mv ShieldPPPs-PT-100A execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;