Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r335-tall-171679082000354.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is SafeBus-COL-03, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r335-tall-171679082000354
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 540K
-rw-r--r-- 1 mcc users 7.9K Apr 12 14:41 CTLCardinality.txt
-rw-r--r-- 1 mcc users 87K Apr 12 14:41 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Apr 12 14:36 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K Apr 12 14:36 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 07:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 23 07:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Apr 23 07:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 12 14:48 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 145K Apr 12 14:48 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Apr 12 14:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Apr 12 14:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 07:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 42K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-00
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-01
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-02
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-03
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-04
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-05
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-06
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-07
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-08
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-09
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-10
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-11
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-12
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-13
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-14
FORMULA_NAME SafeBus-COL-03-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717092431225

FORMULA SafeBus-COL-03-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SafeBus-COL-03-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] SafeBus-COL-03-CTLFireability-2024-00: EFEG false state space /EFEG
[lola] SafeBus-COL-03-CTLFireability-2024-01: CONJ false CTL model checker
[lola] SafeBus-COL-03-CTLFireability-2024-02: CTL true CTL model checker
[lola] SafeBus-COL-03-CTLFireability-2024-03: EF false skeleton: state space
[lola] SafeBus-COL-03-CTLFireability-2024-04: CONJ true CONJ
[lola] SafeBus-COL-03-CTLFireability-2024-05: CTL false CTL model checker
[lola] SafeBus-COL-03-CTLFireability-2024-06: CTL false CTL model checker
[lola] SafeBus-COL-03-CTLFireability-2024-07: CTL false CTL model checker
[lola] SafeBus-COL-03-CTLFireability-2024-08: CTL false CTL model checker
[lola] SafeBus-COL-03-CTLFireability-2024-09: EFAG false tscc_search
[lola] SafeBus-COL-03-CTLFireability-2024-10: CTL true CTL model checker
[lola] SafeBus-COL-03-CTLFireability-2024-11: CTL false CTL model checker
[lola] SafeBus-COL-03-CTLFireability-2024-12: CTL false CTL model checker
[lola] SafeBus-COL-03-CTLFireability-2024-13: EFEG false state space /EFEG
[lola] SafeBus-COL-03-CTLFireability-2024-14: CTL true CTL model checker
[lola] SafeBus-COL-03-CTLFireability-2024-15: DISJ true CTL model checker
[lola]
[lola] Time elapsed: 1 secs. Pages in use: 1

BK_STOP 1717092432213

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains High-Level net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading HL formula in XML format (--xmlformula)
[lola][I] reading formula from CTLFireability.xml
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 69 (type SKEL/FNDP) for 13 SafeBus-COL-03-CTLFireability-2024-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 70 (type SKEL/EQUN) for 13 SafeBus-COL-03-CTLFireability-2024-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 71 (type SKEL/SRCH) for 13 SafeBus-COL-03-CTLFireability-2024-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 73 (type SKEL/FNDP) for 53 SafeBus-COL-03-CTLFireability-2024-15
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 71 (type SKEL/SRCH) for SafeBus-COL-03-CTLFireability-2024-03
[lola][I] result : false
[lola][I] markings : 102
[lola][I] fired transitions : 163
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 69 (type FNDP) for SafeBus-COL-03-CTLFireability-2024-03 (obsolete)
[lola][W] CANCELED task # 70 (type EQUN) for SafeBus-COL-03-CTLFireability-2024-03 (obsolete)
[lola][I] LAUNCH task # 74 (type SKEL/EQUN) for 53 SafeBus-COL-03-CTLFireability-2024-15
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 75 (type SKEL/SRCH) for 53 SafeBus-COL-03-CTLFireability-2024-15
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 69 (type SKEL/FNDP) for SafeBus-COL-03-CTLFireability-2024-03
[lola][I] result : unknown
[lola][I] tried executions : 2
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 75 (type SKEL/SRCH) for SafeBus-COL-03-CTLFireability-2024-15
[lola][I] result : true
[lola][I] markings : 4
[lola][I] fired transitions : 3
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 73 (type FNDP) for SafeBus-COL-03-CTLFireability-2024-15 (obsolete)
[lola][W] CANCELED task # 74 (type EQUN) for SafeBus-COL-03-CTLFireability-2024-15 (obsolete)
[lola][I] FINISHED task # 73 (type SKEL/FNDP) for SafeBus-COL-03-CTLFireability-2024-15
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] Places: 60, Transitions: 97
[lola][I] FINISHED task # 70 (type SKEL/EQUN) for SafeBus-COL-03-CTLFireability-2024-03
[lola][I] result : false
[lola][I] FINISHED task # 74 (type SKEL/EQUN) for SafeBus-COL-03-CTLFireability-2024-15
[lola][I] result : true
[lola][I] Rule S: 6 transitions removed,3 places removed
[lola][I] planning for SafeBus-COL-03-CTLFireability-2024-03 stopped (result already fixed).
[lola][W] findlow criterion violated for transition 11
[lola][I] LAUNCH task # 11 (type EXCL) for 10 SafeBus-COL-03-CTLFireability-2024-02
[lola][I] time limit : 171 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 79 (type EQUN) for 0 SafeBus-COL-03-CTLFireability-2024-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 81 (type EQUN) for 0 SafeBus-COL-03-CTLFireability-2024-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 11 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-02
[lola][I] result : true
[lola][I] markings : 4650
[lola][I] fired transitions : 45426
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 58 (type EXCL) for 53 SafeBus-COL-03-CTLFireability-2024-15
[lola][I] time limit : 189 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 87 (type FNDP) for 53 SafeBus-COL-03-CTLFireability-2024-15
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 58 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-15
[lola][I] result : false
[lola][I] markings : 259
[lola][I] fired transitions : 405
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 87 (type FNDP) for SafeBus-COL-03-CTLFireability-2024-15 (obsolete)
[lola][I] LAUNCH task # 51 (type EXCL) for 50 SafeBus-COL-03-CTLFireability-2024-14
[lola][I] time limit : 211 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 94 (type EQUN) for 35 SafeBus-COL-03-CTLFireability-2024-09
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 87 (type FNDP) for SafeBus-COL-03-CTLFireability-2024-15
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 79 (type EQUN) for SafeBus-COL-03-CTLFireability-2024-00
[lola][I] result : true
[lola][I] LAUNCH task # 86 (type EQUN) for 47 SafeBus-COL-03-CTLFireability-2024-13
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][W] findlow criterion violated for transition 10
[lola][I] FINISHED task # 51 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-14
[lola][I] result : true
[lola][I] markings : 4650
[lola][I] fired transitions : 69333
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 45 (type EXCL) for 44 SafeBus-COL-03-CTLFireability-2024-12
[lola][I] time limit : 225 sec
[lola][I] memory limit: 2000 pages
[lola][W] findlow criterion violated for transition 2
[lola][I] FINISHED task # 45 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-12
[lola][I] result : false
[lola][I] markings : 4650
[lola][I] fired transitions : 66881
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 39 (type EXCL) for 38 SafeBus-COL-03-CTLFireability-2024-10
[lola][I] time limit : 240 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 39 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-10
[lola][I] result : true
[lola][I] markings : 4650
[lola][I] fired transitions : 28772
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 33 (type EXCL) for 32 SafeBus-COL-03-CTLFireability-2024-08
[lola][I] time limit : 257 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 33 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-08
[lola][I] result : false
[lola][I] markings : 3070
[lola][I] fired transitions : 6842
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 30 (type EXCL) for 29 SafeBus-COL-03-CTLFireability-2024-07
[lola][I] time limit : 276 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 30 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-07
[lola][I] result : false
[lola][I] markings : 4650
[lola][I] fired transitions : 30667
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 27 (type EXCL) for 26 SafeBus-COL-03-CTLFireability-2024-06
[lola][I] time limit : 300 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 27 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-06
[lola][I] result : false
[lola][I] markings : 4650
[lola][I] fired transitions : 12933
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 24 (type EXCL) for 23 SafeBus-COL-03-CTLFireability-2024-05
[lola][I] time limit : 327 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 24 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-05
[lola][I] result : false
[lola][I] markings : 4650
[lola][I] fired transitions : 18023
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 21 (type EXCL) for 16 SafeBus-COL-03-CTLFireability-2024-04
[lola][I] time limit : 360 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 21 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-04
[lola][I] result : true
[lola][I] markings : 4650
[lola][I] fired transitions : 47971
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 19 (type EXCL) for 16 SafeBus-COL-03-CTLFireability-2024-04
[lola][I] time limit : 400 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 19 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-04
[lola][I] result : true
[lola][I] markings : 4650
[lola][I] fired transitions : 21704
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 8 (type EXCL) for 3 SafeBus-COL-03-CTLFireability-2024-01
[lola][I] time limit : 449 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 8 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-01
[lola][I] result : false
[lola][I] markings : 1287
[lola][I] fired transitions : 2698
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 82 (type EXCL) for 47 SafeBus-COL-03-CTLFireability-2024-13
[lola][I] time limit : 599 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 82 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-13
[lola][I] result : false
[lola][I] markings : 3714
[lola][I] fired transitions : 9351
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 86 (type EQUN) for SafeBus-COL-03-CTLFireability-2024-13 (obsolete)
[lola][I] LAUNCH task # 76 (type EXCL) for 0 SafeBus-COL-03-CTLFireability-2024-00
[lola][I] time limit : 899 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 96 (type EQUN) for 35 SafeBus-COL-03-CTLFireability-2024-09
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][W] findlow criterion violated for transition 7
[lola][I] FINISHED task # 76 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-00
[lola][I] result : false
[lola][I] markings : 4470
[lola][I] fired transitions : 19638
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 81 (type EQUN) for SafeBus-COL-03-CTLFireability-2024-00 (obsolete)
[lola][I] LAUNCH task # 89 (type EXCL) for 35 SafeBus-COL-03-CTLFireability-2024-09
[lola][I] time limit : 1199 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 89 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-09
[lola][I] result : true
[lola][I] markings : 3786
[lola][I] fired transitions : 8478
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 94 (type EQUN) for SafeBus-COL-03-CTLFireability-2024-09 (obsolete)
[lola][W] CANCELED task # 96 (type EQUN) for SafeBus-COL-03-CTLFireability-2024-09 (obsolete)
[lola][I] LAUNCH task # 66 (type EXCL) for 53 SafeBus-COL-03-CTLFireability-2024-15
[lola][I] time limit : 1799 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 66 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-15
[lola][I] result : true
[lola][I] markings : 18
[lola][I] fired transitions : 18
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 42 (type EXCL) for 41 SafeBus-COL-03-CTLFireability-2024-11
[lola][I] time limit : 3599 sec
[lola][I] memory limit: 2000 pages
[lola][W] findlow criterion violated for transition 8
[lola][I] FINISHED task # 42 (type EXCL) for SafeBus-COL-03-CTLFireability-2024-11
[lola][I] result : false
[lola][I] markings : 4650
[lola][I] fired transitions : 12890
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SafeBus-COL-03"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is SafeBus-COL-03, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r335-tall-171679082000354"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SafeBus-COL-03.tgz
mv SafeBus-COL-03 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;