MCC'2024- Execution of r335-tall-171679081900332

About the Execution of LoLA for RwMutex-PT-r0500w0010

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16189.319	140975.00	146207.00	556.60	FFF?????????????	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r335-tall-171679081900332.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is RwMutex-PT-r0500w0010, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r335-tall-171679081900332
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.7M
-rw-r--r-- 1 mcc users 8.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 34K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 23 07:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 07:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 23 07:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 13 06:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 161K Apr 13 06:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 15K Apr 13 06:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 136K Apr 13 06:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 11 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 1.1M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-00
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-01
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-02
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-03
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-04
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-05
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-06
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-07
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-08
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-09
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-10
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-11
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-12
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-13
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-14
FORMULA_NAME RwMutex-PT-r0500w0010-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717091905250

FORMULA RwMutex-PT-r0500w0010-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0500w0010-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0500w0010-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717092046225

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 56 (type SKEL/SRCH) for 9 RwMutex-PT-r0500w0010-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type SKEL/SRCH) for RwMutex-PT-r0500w0010-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 501
[[35mlola[0m][I] fired transitions : 501
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 RwMutex-PT-r0500w0010-LTLFireability-00
[[35mlola[0m][I] time limit : 133 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 57 (type SKEL/SRCH) for 53 RwMutex-PT-r0500w0010-LTLFireability-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type SKEL/SRCH) for RwMutex-PT-r0500w0010-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 505
[[35mlola[0m][I] fired transitions : 506
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 RwMutex-PT-r0500w0010-LTLFireability-02
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 RwMutex-PT-r0500w0010-LTLFireability-01
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 14
[[35mlola[0m][I] fired transitions : 254
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 21 RwMutex-PT-r0500w0010-LTLFireability-07
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 21 RwMutex-PT-r0500w0010-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN) for 35 RwMutex-PT-r0500w0010-LTLFireability-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 15 RwMutex-PT-r0500w0010-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 62 (type EQUN) for RwMutex-PT-r0500w0010-LTLFireability-07 (obsolete)
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL) for 35 RwMutex-PT-r0500w0010-LTLFireability-09
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 62 (type EQUN) for RwMutex-PT-r0500w0010-LTLFireability-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 64 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 67 (type EQUN) for RwMutex-PT-r0500w0010-LTLFireability-09 (obsolete)
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 RwMutex-PT-r0500w0010-LTLFireability-04
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 23
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 69 (type EXCL) for 15 RwMutex-PT-r0500w0010-LTLFireability-05
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 69 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 72 (type EQUN) for RwMutex-PT-r0500w0010-LTLFireability-05 (obsolete)
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 21 RwMutex-PT-r0500w0010-LTLFireability-07
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for RwMutex-PT-r0500w0010-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 RwMutex-PT-r0500w0010-LTLFireability-03
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 67 (type EQUN) for RwMutex-PT-r0500w0010-LTLFireability-09
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 2/359 2/2000 RwMutex-PT-r0500w0010-LTLFireability-03 239867 m, 47973 m/sec, 871232 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 276501
[[35mlola[0m][I] fired transitions : 1004616
[[35mlola[0m][I] time used : 3
[[35mlola[0m][I] memory pages used : 3
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 RwMutex-PT-r0500w0010-LTLFireability-15
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 80347
[[35mlola[0m][I] fired transitions : 291756
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 RwMutex-PT-r0500w0010-LTLFireability-14
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 RwMutex-PT-r0500w0010-LTLFireability-13
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for RwMutex-PT-r0500w0010-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 18
[[35mlola[0m][I] fired transitions : 18
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 RwMutex-PT-r0500w0010-LTLFireability-12
[[35mlola[0m][I] time limit : 598 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 3/598 3/2000 RwMutex-PT-r0500w0010-LTLFireability-12 334617 m, 66923 m/sec, 1304904 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 8/598 6/2000 RwMutex-PT-r0500w0010-LTLFireability-12 636442 m, 60365 m/sec, 3553099 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 13/598 8/2000 RwMutex-PT-r0500w0010-LTLFireability-12 929328 m, 58577 m/sec, 5794244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 18/598 11/2000 RwMutex-PT-r0500w0010-LTLFireability-12 1192896 m, 52713 m/sec, 8100131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 23/598 13/2000 RwMutex-PT-r0500w0010-LTLFireability-12 1456190 m, 52658 m/sec, 10426565 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 28/598 15/2000 RwMutex-PT-r0500w0010-LTLFireability-12 1731301 m, 55022 m/sec, 12748897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 33/598 17/2000 RwMutex-PT-r0500w0010-LTLFireability-12 2001700 m, 54079 m/sec, 15103808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 38/598 20/2000 RwMutex-PT-r0500w0010-LTLFireability-12 2257552 m, 51170 m/sec, 17470742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 43/598 22/2000 RwMutex-PT-r0500w0010-LTLFireability-12 2509746 m, 50438 m/sec, 19838722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 48/598 24/2000 RwMutex-PT-r0500w0010-LTLFireability-12 2776081 m, 53267 m/sec, 22198818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 53/598 27/2000 RwMutex-PT-r0500w0010-LTLFireability-12 3053692 m, 55522 m/sec, 24511145 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 58/598 29/2000 RwMutex-PT-r0500w0010-LTLFireability-12 3325560 m, 54373 m/sec, 26855181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 63/598 31/2000 RwMutex-PT-r0500w0010-LTLFireability-12 3571128 m, 49113 m/sec, 29222845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 68/598 33/2000 RwMutex-PT-r0500w0010-LTLFireability-12 3853497 m, 56473 m/sec, 31513161 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 73/598 36/2000 RwMutex-PT-r0500w0010-LTLFireability-12 4115523 m, 52405 m/sec, 33868347 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 78/598 38/2000 RwMutex-PT-r0500w0010-LTLFireability-12 4362926 m, 49480 m/sec, 36239360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 83/598 40/2000 RwMutex-PT-r0500w0010-LTLFireability-12 4595818 m, 46578 m/sec, 38636260 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 88/598 42/2000 RwMutex-PT-r0500w0010-LTLFireability-12 4836859 m, 48208 m/sec, 41017749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 93/598 44/2000 RwMutex-PT-r0500w0010-LTLFireability-12 5097660 m, 52160 m/sec, 43379318 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 98/598 46/2000 RwMutex-PT-r0500w0010-LTLFireability-12 5360185 m, 52505 m/sec, 45721648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 103/598 48/2000 RwMutex-PT-r0500w0010-LTLFireability-12 5607094 m, 49381 m/sec, 48097918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 108/598 51/2000 RwMutex-PT-r0500w0010-LTLFireability-12 5861751 m, 50931 m/sec, 50441639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 113/598 53/2000 RwMutex-PT-r0500w0010-LTLFireability-12 6095886 m, 46827 m/sec, 52832639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 118/598 55/2000 RwMutex-PT-r0500w0010-LTLFireability-12 6352176 m, 51258 m/sec, 55157833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 123/598 57/2000 RwMutex-PT-r0500w0010-LTLFireability-12 6589950 m, 47554 m/sec, 57551151 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mRwMutex-PT-r0500w0010-LTLFireability-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRwMutex-PT-r0500w0010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RwMutex-PT-r0500w0010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 LTL EXCL 128/598 59/2000 RwMutex-PT-r0500w0010-LTLFireability-12 6826693 m, 47348 m/sec, 59938421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0500w0010"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is RwMutex-PT-r0500w0010, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r335-tall-171679081900332"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0500w0010.tgz
mv RwMutex-PT-r0500w0010 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;