fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r335-tall-171679081900330
Last Updated
July 7, 2024

About the Execution of LoLA for RwMutex-PT-r0500w0010

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16101.012 117692.00 122809.00 415.50 [undef] Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r335-tall-171679081900330.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is RwMutex-PT-r0500w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r335-tall-171679081900330
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.7M
-rw-r--r-- 1 mcc users 8.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 34K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 23 07:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 07:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 23 07:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 13 06:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 161K Apr 13 06:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 15K Apr 13 06:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 136K Apr 13 06:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 11 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 1.1M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-00
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-01
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-02
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-03
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-04
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-05
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-06
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-07
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-08
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-09
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-10
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2024-11
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2023-12
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2023-13
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2023-14
FORMULA_NAME RwMutex-PT-r0500w0010-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717091796281


BK_STOP 1717091913973

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 28 (type EXCL) for 27 RwMutex-PT-r0500w0010-CTLFireability-2024-09
[lola][I] time limit : 224 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 3/224 1/2000 RwMutex-PT-r0500w0010-CTLFireability-2024-09 187743 m, 37548 m/sec, 681637 t fired, .
[lola][.]
[lola][.] Time elapsed: 9 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 28 (type EXCL) for RwMutex-PT-r0500w0010-CTLFireability-2024-09
[lola][I] result : false
[lola][I] markings : 412746
[lola][I] fired transitions : 1866728
[lola][I] time used : 6
[lola][I] memory pages used : 3
[lola][I] LAUNCH task # 46 (type EXCL) for 45 RwMutex-PT-r0500w0010-CTLFireability-2023-15
[lola][I] time limit : 239 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 46 (type EXCL) for RwMutex-PT-r0500w0010-CTLFireability-2023-15
[lola][I] result : false
[lola][I] markings : 2
[lola][I] fired transitions : 9
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 40 (type EXCL) for 39 RwMutex-PT-r0500w0010-CTLFireability-2023-13
[lola][I] time limit : 256 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 2/256 1/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 54303 m, 10860 m/sec, 250549 t fired, .
[lola][.]
[lola][.] Time elapsed: 14 secs. Pages in use: 3
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 7/256 2/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 283672 m, 45873 m/sec, 1313954 t fired, .
[lola][.]
[lola][.] Time elapsed: 19 secs. Pages in use: 3
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 12/256 3/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 481225 m, 39510 m/sec, 2828380 t fired, .
[lola][.]
[lola][.] Time elapsed: 24 secs. Pages in use: 3
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 17/256 4/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 661324 m, 36019 m/sec, 4396158 t fired, .
[lola][.]
[lola][.] Time elapsed: 29 secs. Pages in use: 4
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 22/256 5/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 843444 m, 36424 m/sec, 5964067 t fired, .
[lola][.]
[lola][.] Time elapsed: 34 secs. Pages in use: 5
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 27/256 7/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 1016657 m, 34642 m/sec, 7558736 t fired, .
[lola][.]
[lola][.] Time elapsed: 39 secs. Pages in use: 7
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 32/256 8/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 1183455 m, 33359 m/sec, 9183049 t fired, .
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 37/256 9/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 1350540 m, 33417 m/sec, 10802375 t fired, .
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 42/256 10/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 1512996 m, 32491 m/sec, 12437560 t fired, .
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 47/256 11/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 1683084 m, 34017 m/sec, 14040770 t fired, .
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 52/256 12/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 1850937 m, 33570 m/sec, 15638208 t fired, .
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 57/256 13/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 2017193 m, 33251 m/sec, 17253364 t fired, .
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 62/256 14/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 2178210 m, 32203 m/sec, 18890134 t fired, .
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 67/256 15/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 2336034 m, 31564 m/sec, 20549291 t fired, .
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 72/256 16/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 2493716 m, 31536 m/sec, 22203880 t fired, .
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2023-14: SP ACTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 77/256 17/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 2663522 m, 33961 m/sec, 23836238 t fired, .
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[lola][.] RwMutex-PT-r0500w0010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 CTL EXCL 82/256 18/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 2826429 m, 32581 m/sec, 25491872 t fired, .
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[lola][.] 40 CTL EXCL 87/256 19/2000 RwMutex-PT-r0500w0010-CTLFireability-2023-13 3000302 m, 34774 m/sec, 27082653 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 404 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0500w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is RwMutex-PT-r0500w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r335-tall-171679081900330"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0500w0010.tgz
mv RwMutex-PT-r0500w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;