Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r335-tall-171679081900306.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is RwMutex-PT-r0010w2000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r335-tall-171679081900306
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.1M
-rw-r--r-- 1 mcc users 5.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 60K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 23 07:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 23 07:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 23 07:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 13 14:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 124K Apr 13 14:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 13 12:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 103K Apr 13 12:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 11 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 3.6M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-00
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-01
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-02
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-03
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-04
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-05
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-06
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-07
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-08
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-09
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-10
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2024-11
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2023-12
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2023-13
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2023-14
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717091611201

FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2023-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2023-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0010w2000-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-00: CTL false CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-01: CTL true CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-02: CTL false CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-03: INITIAL false preprocessing
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-04: CTL true CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-05: CTL false CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-06: CTL true CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-07: CTL false CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-08: EFAG false tscc_search
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-09: CTL true CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-10: CTL false CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2024-11: CTL false CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2023-12: CTL true CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2023-13: CTL false CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2023-14: CTL true CTL model checker
[lola] RwMutex-PT-r0010w2000-CTLFireability-2023-15: CTL true CTL model checker
[lola]
[lola] Time elapsed: 24 secs. Pages in use: 1

BK_STOP 1717091635761

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 10 (type CNST) for 9 RwMutex-PT-r0010w2000-CTLFireability-2024-03
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 10 (type CNST) for RwMutex-PT-r0010w2000-CTLFireability-2024-03
[lola][I] result : false
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-03: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-08: EFAG 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 9 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-03: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-08: EFAG 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-09: CTL 1 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 14 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 28 (type EXCL) for 27 RwMutex-PT-r0010w2000-CTLFireability-2024-09
[lola][I] time limit : 239 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 28 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2024-09
[lola][I] result : true
[lola][I] markings : 2011
[lola][I] fired transitions : 8043
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 43 (type EXCL) for 42 RwMutex-PT-r0010w2000-CTLFireability-2023-14
[lola][I] time limit : 275 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 43 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2023-14
[lola][I] result : true
[lola][I] markings : 2011
[lola][I] fired transitions : 4021
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 46 (type EXCL) for 45 RwMutex-PT-r0010w2000-CTLFireability-2023-15
[lola][I] time limit : 298 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 52 (type EQUN) for 24 RwMutex-PT-r0010w2000-CTLFireability-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 54 (type EQUN) for 24 RwMutex-PT-r0010w2000-CTLFireability-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 46 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2023-15
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 6
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 40 (type EXCL) for 39 RwMutex-PT-r0010w2000-CTLFireability-2023-13
[lola][I] time limit : 298 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 40 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2023-13
[lola][I] result : false
[lola][I] markings : 3024
[lola][I] fired transitions : 14241
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 37 (type EXCL) for 36 RwMutex-PT-r0010w2000-CTLFireability-2023-12
[lola][I] time limit : 325 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 37 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2023-12
[lola][I] result : true
[lola][I] markings : 2009
[lola][I] fired transitions : 2008
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 34 (type EXCL) for 33 RwMutex-PT-r0010w2000-CTLFireability-2024-11
[lola][I] time limit : 358 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 52 (type EQUN) for RwMutex-PT-r0010w2000-CTLFireability-2024-08
[lola][I] result : true
[lola][I] FINISHED task # 54 (type EQUN) for RwMutex-PT-r0010w2000-CTLFireability-2024-08
[lola][I] result : unknown
[lola][I] FINISHED task # 34 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2024-11
[lola][I] result : false
[lola][I] markings : 2020
[lola][I] fired transitions : 40399
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 31 (type EXCL) for 30 RwMutex-PT-r0010w2000-CTLFireability-2024-10
[lola][I] time limit : 398 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 31 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2024-10
[lola][I] result : false
[lola][I] markings : 3024
[lola][I] fired transitions : 23057
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 22 (type EXCL) for 21 RwMutex-PT-r0010w2000-CTLFireability-2024-07
[lola][I] time limit : 447 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 22 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2024-07
[lola][I] result : false
[lola][I] markings : 3024
[lola][I] fired transitions : 33722
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 19 (type EXCL) for 18 RwMutex-PT-r0010w2000-CTLFireability-2024-06
[lola][I] time limit : 511 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-03: INITIAL false preprocessing
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-07: CTL false CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-10: CTL false CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-13: CTL false CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-14: CTL true CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-08: EFAG 0 1 0 0 3 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 1/511 1/2000 RwMutex-PT-r0010w2000-CTLFireability-2024-06 1515 m, 303 m/sec, 7398 t fired, .
[lola][.]
[lola][.] Time elapsed: 19 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 19 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2024-06
[lola][I] result : true
[lola][I] markings : 3024
[lola][I] fired transitions : 20817
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 16 (type EXCL) for 15 RwMutex-PT-r0010w2000-CTLFireability-2024-05
[lola][I] time limit : 596 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 16 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2024-05
[lola][I] result : false
[lola][I] markings : 2011
[lola][I] fired transitions : 8066
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 7 (type EXCL) for 6 RwMutex-PT-r0010w2000-CTLFireability-2024-02
[lola][I] time limit : 716 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 7 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2024-02
[lola][I] result : false
[lola][I] markings : 3024
[lola][I] fired transitions : 17264
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 4 (type EXCL) for 3 RwMutex-PT-r0010w2000-CTLFireability-2024-01
[lola][I] time limit : 895 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 4 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2024-01
[lola][I] result : true
[lola][I] markings : 3024
[lola][I] fired transitions : 14240
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 1 (type EXCL) for 0 RwMutex-PT-r0010w2000-CTLFireability-2024-00
[lola][I] time limit : 1193 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2024-00
[lola][I] result : false
[lola][I] markings : 3024
[lola][I] fired transitions : 14242
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 49 (type EXCL) for 24 RwMutex-PT-r0010w2000-CTLFireability-2024-08
[lola][I] time limit : 1790 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-00: CTL false CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-01: CTL true CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-02: CTL false CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-03: INITIAL false preprocessing
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-07: CTL false CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-09: CTL true CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-10: CTL false CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-11: CTL false CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-12: CTL true CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-13: CTL false CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-14: CTL true CTL model checker
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2023-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] RwMutex-PT-r0010w2000-CTLFireability-2024-08: EFAG 0 0 1 0 3 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 AGEF EXCL 4/1790 1/2000 RwMutex-PT-r0010w2000-CTLFireability-2024-08 1870 m, 374 m/sec, 3737 t fired, .
[lola][.]
[lola][.] Time elapsed: 24 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 49 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2024-08
[lola][I] result : true
[lola][I] markings : 2011
[lola][I] fired transitions : 4020
[lola][I] time used : 4
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 13 (type EXCL) for 12 RwMutex-PT-r0010w2000-CTLFireability-2024-04
[lola][I] time limit : 3576 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 13 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-2024-04
[lola][I] result : true
[lola][I] markings : 3024
[lola][I] fired transitions : 17266
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0010w2000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is RwMutex-PT-r0010w2000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r335-tall-171679081900306"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0010w2000.tgz
mv RwMutex-PT-r0010w2000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;