About the Execution of LoLA for ResAllocation-PT-R020C002
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3911.523 | 245044.00 | 249068.00 | 752.80 | FFTTFFFFFFTFTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662341400866.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ResAllocation-PT-R020C002, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662341400866
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 576K
-rw-r--r-- 1 mcc users 9.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 100K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:48 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 07:48 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 07:48 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 23 07:48 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.7K Apr 11 23:25 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 93K Apr 11 23:25 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 11 23:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 96K Apr 11 23:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 07:48 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:48 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 9 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 85K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-00
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-01
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-02
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-03
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-04
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-05
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-06
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-07
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-08
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-09
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-10
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2024-11
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2023-12
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2023-13
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2023-14
FORMULA_NAME ResAllocation-PT-R020C002-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717358793265
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R020C002-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mResAllocation-PT-R020C002-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mResAllocation-PT-R020C002-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2024-04: DISJ false DISJ[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2024-09: F false state space / EG[0m
[[35mlola[0m] [1m[32mResAllocation-PT-R020C002-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mResAllocation-PT-R020C002-CTLFireability-2023-12: EG true state space / EG[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mResAllocation-PT-R020C002-CTLFireability-2023-15: AGAF false state space /EFEG[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 245 secs. Pages in use: 49
BK_STOP 1717359038309
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 ResAllocation-PT-R020C002-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type EQUN) for 12 ResAllocation-PT-R020C002-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type EQUN) for 12 ResAllocation-PT-R020C002-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 62 (type FNDP) for 12 ResAllocation-PT-R020C002-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type EQUN) for ResAllocation-PT-R020C002-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 62 (type FNDP) for ResAllocation-PT-R020C002-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 49 ResAllocation-PT-R020C002-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type EQUN) for 49 ResAllocation-PT-R020C002-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type EQUN) for ResAllocation-PT-R020C002-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 40 ResAllocation-PT-R020C002-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 77 (type EQUN) for ResAllocation-PT-R020C002-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 78 (type EQUN) for 31 ResAllocation-PT-R020C002-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for ResAllocation-PT-R020C002-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for ResAllocation-PT-R020C002-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 78 (type EQUN) for ResAllocation-PT-R020C002-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-04: DISJ 0 1 0 0 5 0 0 2
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-09: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2023-12: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2023-15: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 5/225 12/2000 ResAllocation-PT-R020C002-CTLFireability-2024-02 2827022 m, 565404 m/sec, 10673241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-04: DISJ 0 1 0 0 5 0 0 2
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-09: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2023-12: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2023-15: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 10/225 26/2000 ResAllocation-PT-R020C002-CTLFireability-2024-02 6140687 m, 662733 m/sec, 20786300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for ResAllocation-PT-R020C002-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7834140
[[35mlola[0m][I] fired transitions : 29251542
[[35mlola[0m][I] time used : 14
[[35mlola[0m][I] memory pages used : 33
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 ResAllocation-PT-R020C002-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for ResAllocation-PT-R020C002-CTLFireability-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 145
[[35mlola[0m][I] fired transitions : 360
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 ResAllocation-PT-R020C002-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R020C002-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R020C002-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-04: DISJ 0 1 0 0 5 0 0 2
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-09: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2023-12: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R020C002-CTLFireability-2023-15: AGAF 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 1/256 2/2000 ResAllocation-PT-R020C002-CTLFireability-2024-11 344822 m, 68964 m/sec, 1679555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R020C002-CTLFireability-2024-02: CTL true CTL model checker[0m
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[[35mlola[0m][.] 47 CTL EXCL 11/3401 18/2000 ResAllocation-PT-R020C002-CTLFireability-2023-14 4172640 m, 373499 m/sec, 23223734 t fired, .
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[[35mlola[0m][.] 47 CTL EXCL 16/3401 25/2000 ResAllocation-PT-R020C002-CTLFireability-2023-14 5988354 m, 363142 m/sec, 33257691 t fired, .
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[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R020C002"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R020C002, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662341400866"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R020C002.tgz
mv ResAllocation-PT-R020C002 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;