fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r313-tall-171662341300810
Last Updated
July 7, 2024

About the Execution of LoLA for ResAllocation-PT-R003C015

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15414.743 3600000.00 1416112.00 11363.80 ???????FT?F????? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r313-tall-171662341300810.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ResAllocation-PT-R003C015, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662341300810
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 628K
-rw-r--r-- 1 mcc users 7.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 71K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 71K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 07:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 07:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 11 23:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 143K Apr 11 23:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 11 23:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 96K Apr 11 23:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 07:47 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:47 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 9 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 107K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-00
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-01
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-02
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-03
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-04
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-05
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-06
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-07
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-08
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-09
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-10
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2024-11
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2023-12
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2023-13
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2023-14
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717354940175

FORMULA ResAllocation-PT-R003C015-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 39 (type CNST) for 38 ResAllocation-PT-R003C015-CTLFireability-2024-10
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 39 (type CNST) for ResAllocation-PT-R003C015-CTLFireability-2024-10
[lola][I] result : false
[lola][I] LAUNCH task # 33 (type EXCL) for 32 ResAllocation-PT-R003C015-CTLFireability-2024-08
[lola][I] time limit : 171 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 33 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-2024-08
[lola][I] result : true
[lola][I] markings : 866
[lola][I] fired transitions : 4650
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 19 (type EXCL) for 18 ResAllocation-PT-R003C015-CTLFireability-2024-06
[lola][I] time limit : 189 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 59 (type FNDP) for 21 ResAllocation-PT-R003C015-CTLFireability-2024-07
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 60 (type EQUN) for 21 ResAllocation-PT-R003C015-CTLFireability-2024-07
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 59 (type FNDP) for ResAllocation-PT-R003C015-CTLFireability-2024-07
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 60 (type EQUN) for ResAllocation-PT-R003C015-CTLFireability-2024-07 (obsolete)
[lola][I] FINISHED task # 60 (type EQUN) for ResAllocation-PT-R003C015-CTLFireability-2024-07
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-07: CONJ false findpath
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 5/276 4/2000 ResAllocation-PT-R003C015-CTLFireability-2024-06 936699 m, 187339 m/sec, 9135365 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 4
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-07: CONJ false findpath
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 10/276 8/2000 ResAllocation-PT-R003C015-CTLFireability-2024-06 1737580 m, 160176 m/sec, 17983737 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 8
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-07: CONJ false findpath
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 15/276 11/2000 ResAllocation-PT-R003C015-CTLFireability-2024-06 2585344 m, 169552 m/sec, 25746209 t fired, .
[lola][.]
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-07: CONJ false findpath
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 20/276 14/2000 ResAllocation-PT-R003C015-CTLFireability-2024-06 3333340 m, 149599 m/sec, 34409246 t fired, .
[lola][.]
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-07: CONJ false findpath
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 25/276 17/2000 ResAllocation-PT-R003C015-CTLFireability-2024-06 4041345 m, 141601 m/sec, 42833234 t fired, .
[lola][.]
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-07: CONJ false findpath
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 30/276 20/2000 ResAllocation-PT-R003C015-CTLFireability-2024-06 4772059 m, 146142 m/sec, 51081315 t fired, .
[lola][.]
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-07: CONJ false findpath
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 35/276 23/2000 ResAllocation-PT-R003C015-CTLFireability-2024-06 5470945 m, 139777 m/sec, 58740098 t fired, .
[lola][.]
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-07: CONJ false findpath
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[lola][.] 19 CTL EXCL 40/276 27/2000 ResAllocation-PT-R003C015-CTLFireability-2024-06 6234256 m, 152662 m/sec, 67208191 t fired, .
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[lola][I] LAUNCH task # 42 (type EXCL) for 41 ResAllocation-PT-R003C015-CTLFireability-2024-11
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-07: CONJ false findpath
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-13: CTL true CTL model checker
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[lola][.] 42 CTL EXCL 5/413 7/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 1444758 m, 288951 m/sec, 7878004 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-13: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-14: CTL false CTL model checker
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[lola][.] 42 CTL EXCL 10/413 12/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 2809180 m, 272884 m/sec, 15685667 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL false CTL model checker
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[lola][.] 42 CTL EXCL 15/413 17/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 4023608 m, 242885 m/sec, 23043895 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-07: CONJ false findpath
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL false CTL model checker
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[lola][.] 42 CTL EXCL 20/413 23/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 5321898 m, 259658 m/sec, 30866997 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
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[lola][.] 42 CTL EXCL 25/413 28/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 6509878 m, 237596 m/sec, 37582516 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
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[lola][.] 42 CTL EXCL 30/413 33/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 7696362 m, 237296 m/sec, 43180128 t fired, .
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[lola][.] 42 CTL EXCL 35/413 35/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 8253422 m, 111412 m/sec, 49669729 t fired, .
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[lola][.] 42 CTL EXCL 40/413 39/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 9166415 m, 182598 m/sec, 57777272 t fired, .
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[lola][.] 42 CTL EXCL 45/413 44/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 10392200 m, 245157 m/sec, 65132897 t fired, .
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[lola][.] 42 CTL EXCL 50/413 49/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 11547574 m, 231074 m/sec, 71628274 t fired, .
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[lola][.] 42 CTL EXCL 55/413 52/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 12391938 m, 168872 m/sec, 80266418 t fired, .
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[lola][.] 42 CTL EXCL 60/413 56/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 13182298 m, 158072 m/sec, 87956982 t fired, .
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[lola][.] 42 CTL EXCL 65/413 59/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 13995877 m, 162715 m/sec, 94491302 t fired, .
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[lola][.] 42 CTL EXCL 70/413 62/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 14752768 m, 151378 m/sec, 102644110 t fired, .
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[lola][.] 42 CTL EXCL 75/413 67/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 15760195 m, 201485 m/sec, 110972761 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-13: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-14: CTL false CTL model checker
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[lola][.] 42 CTL EXCL 105/413 88/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 20838353 m, 147851 m/sec, 156757415 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ResAllocation-PT-R003C015-CTLFireability-2023-13: CTL true CTL model checker
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[lola][.] 42 CTL EXCL 110/413 91/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 21608712 m, 154071 m/sec, 163412847 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
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[lola][.] 42 CTL EXCL 115/413 95/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 22491950 m, 176647 m/sec, 169697836 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
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[lola][.] 42 CTL EXCL 120/413 98/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 23250177 m, 151645 m/sec, 175466261 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
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[lola][.] 42 CTL EXCL 125/413 98/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 23277172 m, 5399 m/sec, 182662796 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
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[lola][.] 42 CTL EXCL 130/413 103/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 24408697 m, 226305 m/sec, 190296342 t fired, .
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[lola][.] 42 CTL EXCL 135/413 108/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 25602151 m, 238690 m/sec, 198055676 t fired, .
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[lola][.] 42 CTL EXCL 140/413 112/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 26679488 m, 215467 m/sec, 205230174 t fired, .
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[lola][.] 42 CTL EXCL 150/413 122/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 29026125 m, 221092 m/sec, 220636791 t fired, .
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[lola][.] 42 CTL EXCL 155/413 126/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 30057782 m, 206331 m/sec, 226430060 t fired, .
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[lola][.] 42 CTL EXCL 160/413 130/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 31007931 m, 190029 m/sec, 231849942 t fired, .
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[lola][.] 42 CTL EXCL 165/413 133/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 31529526 m, 104319 m/sec, 238045148 t fired, .
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[lola][.] 42 CTL EXCL 170/413 135/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 32190689 m, 132232 m/sec, 245904859 t fired, .
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[lola][.] 42 CTL EXCL 175/413 140/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 33296407 m, 221143 m/sec, 252953303 t fired, .
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[lola][.] 42 CTL EXCL 180/413 145/2000 ResAllocation-PT-R003C015-CTLFireability-2024-11 34388204 m, 218359 m/sec, 259718499 t fired, .
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[lola][.] 10 CTL EXCL 3/621 2/2000 ResAllocation-PT-R003C015-CTLFireability-2024-03 444999 m, 88999 m/sec, 5057150 t fired, .
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[lola][.] 10 CTL EXCL 8/621 6/2000 ResAllocation-PT-R003C015-CTLFireability-2024-03 1203151 m, 151630 m/sec, 14229553 t fired, .
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[lola][.] 10 CTL EXCL 18/621 12/2000 ResAllocation-PT-R003C015-CTLFireability-2024-03 2651100 m, 148251 m/sec, 32145467 t fired, .
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[lola][.] 10 CTL EXCL 28/621 17/2000 ResAllocation-PT-R003C015-CTLFireability-2024-03 4048811 m, 144851 m/sec, 47981043 t fired, .
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[lola][.] 10 CTL EXCL 53/621 30/2000 ResAllocation-PT-R003C015-CTLFireability-2024-03 7036045 m, 124736 m/sec, 90622936 t fired, .
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[lola][.] 10 CTL EXCL 108/621 58/2000 ResAllocation-PT-R003C015-CTLFireability-2024-03 13733535 m, 115665 m/sec, 180454605 t fired, .
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[lola][.] 10 CTL EXCL 318/621 155/2000 ResAllocation-PT-R003C015-CTLFireability-2024-03 36981387 m, 100919 m/sec, 507163203 t fired, .
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[lola][.] 7 CTL EXCL 5/621 9/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 1908101 m, 381620 m/sec, 9465093 t fired, .
[lola][.] 10 CTL EXCL 5/2485 4/5 ResAllocation-PT-R003C015-CTLFireability-2024-03 805506 m, -14092641 m/sec, 9323333 t fired, .
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[lola][.] 7 CTL EXCL 10/621 16/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 3757280 m, 369835 m/sec, 18920148 t fired, .
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[lola][.] 7 CTL EXCL 15/621 24/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 5514915 m, 351527 m/sec, 28566082 t fired, .
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[lola][.] 7 CTL EXCL 20/621 31/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 7248832 m, 346783 m/sec, 37339192 t fired, .
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[lola][.] 7 CTL EXCL 25/621 38/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 9006027 m, 351439 m/sec, 46907461 t fired, .
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[lola][.] 7 CTL EXCL 30/621 45/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 10651692 m, 329133 m/sec, 56232278 t fired, .
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[lola][.] 7 CTL EXCL 60/621 88/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 20744947 m, 330979 m/sec, 110947236 t fired, .
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[lola][.] 7 CTL EXCL 65/621 95/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 22402936 m, 331597 m/sec, 119129793 t fired, .
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[lola][.] 7 CTL EXCL 85/621 120/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 28540647 m, 292818 m/sec, 154428523 t fired, .
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[lola][.] 7 CTL EXCL 110/621 153/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 36343044 m, 267889 m/sec, 199600999 t fired, .
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[lola][.] 7 CTL EXCL 115/621 159/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 37744699 m, 280331 m/sec, 208313514 t fired, .
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[lola][.] 7 CTL EXCL 165/621 225/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 53497658 m, 300974 m/sec, 296290471 t fired, .
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[lola][.] 7 CTL EXCL 170/621 232/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 55166036 m, 333675 m/sec, 305188402 t fired, .
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[lola][.] 7 CTL EXCL 215/621 289/2000 ResAllocation-PT-R003C015-CTLFireability-2024-02 68681798 m, 257882 m/sec, 381439305 t fired, .
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[lola][.] ResAllocation-PT-R003C015-CTLFireability-2024-08: CTL true CTL model checker
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C015"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R003C015, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662341300810"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C015.tgz
mv ResAllocation-PT-R003C015 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;