About the Execution of LoLA for ResAllocation-PT-R003C015
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15655.760 | 3600000.00 | 864177.00 | 10314.90 | ????????????TF?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662341300809.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ResAllocation-PT-R003C015, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662341300809
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 628K
-rw-r--r-- 1 mcc users 7.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 71K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 71K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 07:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 07:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 11 23:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 143K Apr 11 23:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 11 23:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 96K Apr 11 23:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 07:47 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:47 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 9 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 107K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-00
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-01
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-02
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-03
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-04
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-05
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-06
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-07
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-08
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-09
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-10
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2024-11
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2023-12
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2023-13
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2023-14
FORMULA_NAME ResAllocation-PT-R003C015-CTLCardinality-2023-15
=== Now, execution of the tool begins
BK_START 1717354935271
FORMULA ResAllocation-PT-R003C015-CTLCardinality-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLCardinality-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLCardinality-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 49 (type CNST) for 48 ResAllocation-PT-R003C015-CTLCardinality-2023-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 49 (type CNST) for ResAllocation-PT-R003C015-CTLCardinality-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 57 ResAllocation-PT-R003C015-CTLCardinality-2023-15
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 ResAllocation-PT-R003C015-CTLCardinality-2023-13
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 15 (type EXCL) for 12 ResAllocation-PT-R003C015-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 25 ResAllocation-PT-R003C015-CTLCardinality-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type EQUN) for ResAllocation-PT-R003C015-CTLCardinality-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 15 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11620
[[35mlola[0m][I] fired transitions : 43439
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 ResAllocation-PT-R003C015-CTLCardinality-2023-14
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 CTL EXCL 4/239 5/2000 ResAllocation-PT-R003C015-CTLCardinality-2023-14 1144411 m, 228882 m/sec, 6065540 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1640584
[[35mlola[0m][I] fired transitions : 8046189
[[35mlola[0m][I] time used : 6
[[35mlola[0m][I] memory pages used : 7
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 38 ResAllocation-PT-R003C015-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 3/256 2/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 276439 m, 55287 m/sec, 4953580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 8/256 3/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 609391 m, 66590 m/sec, 12757167 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 13/256 4/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 948788 m, 67879 m/sec, 20683133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 18/256 6/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 1270069 m, 64256 m/sec, 28246761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 23/256 7/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 1609810 m, 67948 m/sec, 35272257 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 28/256 8/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 1855519 m, 49141 m/sec, 42597047 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 33/256 10/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 2185164 m, 65929 m/sec, 50594705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 38/256 11/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 2502257 m, 63418 m/sec, 58329728 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 43/256 12/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 2809439 m, 61436 m/sec, 65927604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 48/256 14/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 3119551 m, 62022 m/sec, 72961926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 53/256 15/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 3462412 m, 68572 m/sec, 79858827 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 58/256 16/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 3720064 m, 51530 m/sec, 85743531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 63/256 17/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 4016788 m, 59344 m/sec, 92604440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 68/256 18/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 4100368 m, 16716 m/sec, 98859731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 73/256 18/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 4168986 m, 13723 m/sec, 105796937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 78/256 19/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 4486624 m, 63527 m/sec, 113539398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 83/256 20/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 4758865 m, 54448 m/sec, 121044676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 88/256 22/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 5072202 m, 62667 m/sec, 128787398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 93/256 23/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 5339224 m, 53404 m/sec, 136176207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 98/256 24/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 5647775 m, 61710 m/sec, 143398689 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 103/256 25/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 5836487 m, 37742 m/sec, 150153354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 108/256 26/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 6136506 m, 60003 m/sec, 158019372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 113/256 27/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 6419436 m, 56586 m/sec, 165892608 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 118/256 29/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 6686284 m, 53369 m/sec, 173412707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 123/256 30/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 6937307 m, 50204 m/sec, 180643471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 128/256 31/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 7185243 m, 49587 m/sec, 187223653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 133/256 32/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 7481255 m, 59202 m/sec, 193511462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 138/256 33/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 7733628 m, 50474 m/sec, 199623702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 143/256 34/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 7981014 m, 49477 m/sec, 205920454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 148/256 35/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 8154278 m, 34652 m/sec, 212247911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 153/256 35/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 8227908 m, 14726 m/sec, 218316092 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 158/256 35/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 8291674 m, 12753 m/sec, 225116772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 163/256 37/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 8696014 m, 80868 m/sec, 232812689 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 168/256 38/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 9025544 m, 65906 m/sec, 240565490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 173/256 40/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 9324998 m, 59890 m/sec, 247403502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 178/256 41/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 9606339 m, 56268 m/sec, 255013892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 183/256 42/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 9905683 m, 59868 m/sec, 262454478 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 188/256 43/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 10210185 m, 60900 m/sec, 269661115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 193/256 44/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 10403327 m, 38628 m/sec, 276291712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 198/256 45/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 10710961 m, 61526 m/sec, 283668861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 203/256 47/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 11001877 m, 58183 m/sec, 291056264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 208/256 48/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 11240977 m, 47820 m/sec, 298429491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 213/256 49/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 11468659 m, 45536 m/sec, 305199850 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 218/256 50/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 11702573 m, 46782 m/sec, 312561608 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 223/256 51/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 11956232 m, 50731 m/sec, 319129631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 228/256 51/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 12094443 m, 27642 m/sec, 325505184 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 233/256 52/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 12386833 m, 58478 m/sec, 333165892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 238/256 54/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 12654382 m, 53509 m/sec, 340809354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 243/256 55/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 12906572 m, 50438 m/sec, 348103991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 248/256 56/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 13159542 m, 50594 m/sec, 355265573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 253/256 57/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-10 13398258 m, 47743 m/sec, 361725785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 43 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-10 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ 0 1 0 0 2 1 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 38 ResAllocation-PT-R003C015-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 38 ResAllocation-PT-R003C015-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 3334 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 59
[[35mlola[0m][I] fired transitions : 72
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 43 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-10 (obsolete)
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 ResAllocation-PT-R003C015-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 277 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 278296
[[35mlola[0m][I] fired transitions : 1280184
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 ResAllocation-PT-R003C015-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 303 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 214
[[35mlola[0m][I] fired transitions : 395
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 25 ResAllocation-PT-R003C015-CTLCardinality-2024-07
[[35mlola[0m][I] time limit : 333 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 60
[[35mlola[0m][I] fired transitions : 73
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 ResAllocation-PT-R003C015-CTLCardinality-2024-06
[[35mlola[0m][I] time limit : 370 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 14
[[35mlola[0m][I] fired transitions : 21
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 ResAllocation-PT-R003C015-CTLCardinality-2024-05
[[35mlola[0m][I] time limit : 416 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 59
[[35mlola[0m][I] fired transitions : 72
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 12 ResAllocation-PT-R003C015-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 476 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 ResAllocation-PT-R003C015-CTLCardinality-2024-03
[[35mlola[0m][I] time limit : 555 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 4/555 4/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 766806 m, 153361 m/sec, 7621876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 9/555 7/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 1560196 m, 158678 m/sec, 15937031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 14/555 11/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 2397200 m, 167400 m/sec, 24492096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 19/555 14/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 3142095 m, 148979 m/sec, 32513690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 24/555 16/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 3759166 m, 123414 m/sec, 40235625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 29/555 19/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 4523661 m, 152899 m/sec, 48707427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 34/555 22/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 5226856 m, 140639 m/sec, 56705022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 39/555 25/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 5860285 m, 126685 m/sec, 65253464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 44/555 28/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 6643924 m, 156727 m/sec, 72573389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 49/555 31/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 7209029 m, 113021 m/sec, 80257350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 54/555 33/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 7873352 m, 132864 m/sec, 87697786 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 59/555 37/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 8601613 m, 145652 m/sec, 95581987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 64/555 39/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 9284852 m, 136647 m/sec, 103402457 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 69/555 42/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 10006227 m, 144275 m/sec, 111155872 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 74/555 45/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 10633848 m, 125524 m/sec, 119313043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 79/555 48/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 11239841 m, 121198 m/sec, 126946449 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 346 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 84/555 51/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 11964064 m, 144844 m/sec, 135119307 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 351 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 89/555 53/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 12629950 m, 133177 m/sec, 142556160 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 94/555 56/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 13227172 m, 119444 m/sec, 149815495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 361 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 99/555 59/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 13849944 m, 124554 m/sec, 157950606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 366 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 104/555 61/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 14550923 m, 140195 m/sec, 165935381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 371 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 109/555 64/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 15234733 m, 136762 m/sec, 173709484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 376 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 114/555 67/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 15791311 m, 111315 m/sec, 182028186 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 381 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 119/555 70/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 16471566 m, 136051 m/sec, 189617293 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 386 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 124/555 72/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 17171742 m, 140035 m/sec, 197211674 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 391 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 129/555 74/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 17428773 m, 51406 m/sec, 205088839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 396 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 134/555 76/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 18055556 m, 125356 m/sec, 212046789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 139/555 79/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 18701572 m, 129203 m/sec, 218503126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 144/555 81/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 19324860 m, 124657 m/sec, 225172363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 149/555 85/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 20063983 m, 147824 m/sec, 231736800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 154/555 87/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 20667495 m, 120702 m/sec, 238296343 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 159/555 90/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 21313206 m, 129142 m/sec, 244205052 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 164/555 91/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 21643088 m, 65976 m/sec, 251899372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 169/555 94/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 22370308 m, 145444 m/sec, 260326225 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 174/555 97/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 23059069 m, 137752 m/sec, 268407287 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 179/555 100/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 23797459 m, 147678 m/sec, 276612339 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 446 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 184/555 103/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 24448155 m, 130139 m/sec, 284027612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 189/555 105/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 25047237 m, 119816 m/sec, 291203405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 456 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 194/555 108/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 25612496 m, 113051 m/sec, 298959486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 461 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 199/555 111/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 26261942 m, 129889 m/sec, 307119227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 466 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 204/555 113/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 26824602 m, 112532 m/sec, 314629467 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 471 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 209/555 116/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 27524214 m, 139922 m/sec, 322492911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 476 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 214/555 118/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 28080195 m, 111196 m/sec, 329744761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 481 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 219/555 120/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 28594715 m, 102904 m/sec, 337059253 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 486 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 225/555 123/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 29185957 m, 118248 m/sec, 344294270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 492 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 230/555 125/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 29820817 m, 126972 m/sec, 351903055 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 497 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 235/555 128/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 30463077 m, 128452 m/sec, 359791416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 502 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 240/555 131/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 31070467 m, 121478 m/sec, 367072412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 507 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 245/555 133/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 31677833 m, 121473 m/sec, 375030078 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 512 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 250/555 136/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 32223043 m, 109042 m/sec, 382637207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 517 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 255/555 138/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 32782040 m, 111799 m/sec, 390463781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 522 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 260/555 141/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 33485979 m, 140787 m/sec, 397764020 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 527 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 265/555 143/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 34005991 m, 104002 m/sec, 405187773 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 532 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 270/555 145/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 34548997 m, 108601 m/sec, 412095651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 537 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 275/555 148/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 35243844 m, 138969 m/sec, 420015693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 542 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 280/555 151/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 35990817 m, 149394 m/sec, 427907285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 547 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 285/555 154/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 36700577 m, 141952 m/sec, 435690907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 552 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 290/555 157/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 37341708 m, 128226 m/sec, 443529781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 557 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 295/555 160/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 38061228 m, 143904 m/sec, 450919677 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 562 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 300/555 163/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 38790850 m, 145924 m/sec, 458882031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 567 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 305/555 166/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 39450645 m, 131959 m/sec, 466694695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 572 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 310/555 168/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 40060339 m, 121938 m/sec, 473830292 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 315/555 171/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 40765922 m, 141116 m/sec, 482118369 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 582 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 320/555 175/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 41596351 m, 166085 m/sec, 489239678 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 587 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 325/555 177/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 42238828 m, 128495 m/sec, 496528613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 592 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 330/555 180/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 42839276 m, 120089 m/sec, 504008771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 597 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 335/555 182/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 43416661 m, 115477 m/sec, 510983328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 602 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 340/555 185/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 44128108 m, 142289 m/sec, 519053943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 607 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 345/555 188/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 44789318 m, 132242 m/sec, 526546698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 612 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 350/555 191/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 45430200 m, 128176 m/sec, 534306252 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 617 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 355/555 193/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 46001323 m, 114224 m/sec, 542188687 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 622 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 360/555 196/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 46638942 m, 127523 m/sec, 549384963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 627 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 365/555 199/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 47317735 m, 135758 m/sec, 557067888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 632 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 370/555 201/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 47908309 m, 118114 m/sec, 564735493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 637 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 375/555 204/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 48471359 m, 112610 m/sec, 572201136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 642 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 380/555 206/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 49056434 m, 117015 m/sec, 579562914 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 647 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 385/555 209/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 49672145 m, 123142 m/sec, 587621367 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 652 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 390/555 212/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 50481367 m, 161844 m/sec, 594219002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 657 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 395/555 214/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 51013267 m, 106380 m/sec, 601505315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 662 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 400/555 216/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 51532279 m, 103802 m/sec, 608799930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 667 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 405/555 219/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 52049153 m, 103374 m/sec, 615314719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 672 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 410/555 222/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 52786404 m, 147450 m/sec, 623154940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 677 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 415/555 225/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 53493036 m, 141326 m/sec, 631207813 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 682 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 420/555 227/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 54163081 m, 134009 m/sec, 639117693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 687 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 425/555 230/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 54822496 m, 131883 m/sec, 646877625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 692 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 430/555 233/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 55543283 m, 144157 m/sec, 654852483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 697 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 435/555 236/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 56306769 m, 152697 m/sec, 661809752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 702 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 440/555 239/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 56889755 m, 116597 m/sec, 669461195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 707 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 445/555 241/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 57440500 m, 110149 m/sec, 676696875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 712 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 450/555 243/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 57998821 m, 111664 m/sec, 683810603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 717 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 455/555 246/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 58633812 m, 126998 m/sec, 691527920 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 722 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 460/555 249/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 59258111 m, 124859 m/sec, 699329374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 727 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 465/555 251/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 59868592 m, 122096 m/sec, 706928436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 732 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 470/555 254/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 60439440 m, 114169 m/sec, 714463361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 737 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 475/555 256/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 61014882 m, 115088 m/sec, 722633089 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 742 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 480/555 259/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 61792405 m, 155504 m/sec, 729299930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 747 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 485/555 262/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 62305324 m, 102583 m/sec, 736470666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 752 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 490/555 264/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 62806197 m, 100174 m/sec, 743954461 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 757 secs. Pages in use: 264
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 495/555 266/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 63317863 m, 102333 m/sec, 750502177 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 762 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 500/555 268/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 63904551 m, 117337 m/sec, 757919901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 767 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 505/555 271/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 64480946 m, 115279 m/sec, 765692432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 772 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 510/555 273/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 65075890 m, 118988 m/sec, 772655802 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 777 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 515/555 276/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 65660742 m, 116970 m/sec, 780236128 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 782 secs. Pages in use: 276
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 520/555 278/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 66192620 m, 106375 m/sec, 787649793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 787 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 525/555 280/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 66773386 m, 116153 m/sec, 794724924 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 792 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 530/555 283/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 67335846 m, 112492 m/sec, 802305517 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 797 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 535/555 285/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 67886081 m, 110047 m/sec, 809836141 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 802 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 540/555 287/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 68325557 m, 87895 m/sec, 817530755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 807 secs. Pages in use: 287
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 545/555 289/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 68847316 m, 104351 m/sec, 824038765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 812 secs. Pages in use: 289
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 550/555 291/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 69349249 m, 100386 m/sec, 831902033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 817 secs. Pages in use: 291
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 555/555 293/2000 ResAllocation-PT-R003C015-CTLCardinality-2024-03 69936461 m, 117442 m/sec, 839452453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 822 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 10 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-03 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 827 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 ResAllocation-PT-R003C015-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 554 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 ResAllocation-PT-R003C015-CTLCardinality-2024-03
[[35mlola[0m][I] time limit : 2773 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 105
[[35mlola[0m][I] fired transitions : 136
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 5/554 4/5 ResAllocation-PT-R003C015-CTLCardinality-2024-03 874457 m, -13812400 m/sec, 8632391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 832 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 10 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-03 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 837 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 ResAllocation-PT-R003C015-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 690 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 25 ResAllocation-PT-R003C015-CTLCardinality-2024-07
[[35mlola[0m][I] time limit : 921 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 61 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 ResAllocation-PT-R003C015-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 1381 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 330401
[[35mlola[0m][I] fired transitions : 3201219
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 ResAllocation-PT-R003C015-CTLCardinality-2024-00
[[35mlola[0m][I] time limit : 2762 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for ResAllocation-PT-R003C015-CTLCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 95
[[35mlola[0m][I] fired transitions : 108
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 842 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 847 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 852 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 857 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 862 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 867 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 872 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 877 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 882 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 887 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 892 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 897 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 902 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 907 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 912 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 917 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 922 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 927 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 932 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 937 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 942 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 947 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 952 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 957 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 962 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 967 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 972 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 977 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 982 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 987 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 992 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 997 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1002 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1007 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1012 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1017 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1022 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1027 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1032 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1037 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1042 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1047 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1052 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1057 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1062 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1067 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1072 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1077 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1082 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1087 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1092 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1097 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1102 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1107 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1112 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1117 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1122 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1127 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1132 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1137 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1142 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1147 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1152 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1157 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1162 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1167 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1172 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1177 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1182 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1187 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1192 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1197 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1202 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1207 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1212 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1217 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1222 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1227 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1232 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1237 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1242 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1247 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1252 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1257 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1262 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1267 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1272 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1277 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1282 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1287 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1292 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1297 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1302 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1307 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1312 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1317 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1322 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1327 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1332 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1337 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1342 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1347 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1352 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1357 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1362 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1367 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1372 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1377 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1382 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1387 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1392 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1397 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1402 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1407 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1412 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1417 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1422 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1427 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1432 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1437 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1442 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1447 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1452 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1457 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1462 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1467 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1472 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1477 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1482 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1487 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1492 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1497 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1502 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1507 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1512 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1517 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1522 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1527 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1532 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1537 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1542 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1547 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1552 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1557 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1562 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1567 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1572 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1577 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1582 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1587 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1592 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1597 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1602 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1607 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1612 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1617 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1622 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1627 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1632 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1637 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1642 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1647 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1652 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1657 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1662 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1667 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1672 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1677 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1682 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1687 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1692 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1697 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1702 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1707 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1712 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1717 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1722 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1727 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1732 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1737 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1742 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1747 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1752 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1757 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1762 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1767 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1772 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1777 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1782 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1787 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1792 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1797 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1802 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1807 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1812 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1817 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1822 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1827 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1832 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1837 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1842 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1847 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1852 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1857 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1862 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1867 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1872 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1877 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1882 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1887 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1892 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1897 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1902 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1907 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1912 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1917 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1922 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1927 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1932 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1937 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1942 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1947 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1952 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1957 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1962 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1967 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1972 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-04: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-07: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-10: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mResAllocation-PT-R003C015-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ResAllocation-PT-R003C015-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1977 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mResAllocation-PT-R003C015-CTLCardinality-2024-01: CTL true CTL model checker[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C015"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R003C015, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662341300809"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C015.tgz
mv ResAllocation-PT-R003C015 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;